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MT55L512L18P Datasheet(PDF) 14 Page - Micron Technology

Part No. MT55L512L18P
Description  8Mb ZBT SRAM
Download  30 Pages
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Maker  MICRON [Micron Technology]
Homepage  http://www.micron.com
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MT55L512L18P Datasheet(HTML) 14 Page - Micron Technology

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14
8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L512L18P_2.p65 – Rev. 6/01
©2001, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
BGA PIN DESCRIPTIONS (continued)
x 1 8
x32/x36
SYMBOL TYPE
DESCRIPTION
4 F
4 F
OE#
Input
Output Enable: This active LOW, asynchronous input enables the
data I/O output drivers.
4 B
4 B
ADV#/LD# Input Synchronous Address Advance/Load: When HIGH, this input is
used to advance the internal burst counter, controlling burst
access after the external addressis loaded. When ADV#/LD# is
HIGH, R/W# is ignored. A LOW on ADV#/LD# clocks a new
address at the CLK rising edge.
3 R
3 R
MODE
Input Mode: This input selects the burst sequence. A LOW on this
input selects “linear burst.” NC or HIGH on this input selects
“interleaved burst.” Do not alter input state while device is
operating.
4 A
4 A
N F
Input
No Function: These pins are internally connected to the die and
will have the capacitance of input pins. It is allowable to leave
these pins unconnected or driven by signals. These pins are
reserved for address expansion; 4A becomes an SA at 16Mb
density.
(a) 6F, 6H, 6L,
(a) 6K, 6L,
D Q a
Input/ SRAM Data I/Os: For the x18 version, Byte “a” is DQa’s; Byte “b”
6N, 7E, 7G,
6M, 6N, 7K,
Output is DQb’s. For the x32 and x36 versions, Byte “a” is DQa’s;
7K, 7P
7L, 7N, 7P
Byte “b” is DQb’s; Byte “c” is DQc’s; Byte “d” is DQd’s. Input
(b) 1D, 1H,
(b) 6E, 6F,
D Q b
data must meet setup and hold times around the rising edge of
1L, 1N, 2E,
6G, 6H, 7D,
CLK.
2G, 2K, 2M
7E, 7G, 7H
(c) 1D, 1E,
DQc
1G, 1H, 2E,
2F, 2G, 2H
(d) 1K, 1L,
DQd
1N, 1P, 2K,
2L, 2M, 2N
6D
6P
NF/DQPa
NF/
No Function/Parity Data I/Os: On the x32 version, these are No
2P
6 D
NF/DQPb
I/O
Function (NF). On the x18 version, Byte “a” parity is DQPa; Byte
2D
NF/DQPc
“b” parity is DQPb. On the x36 version, Byte “a” parity is DQPa;
2P
NF/DQPd
Byte “b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity
is DQPd.
2J, 4C, 4J,
2J, 4C, 4J,
VDD
Supply Power Supply: See DC Electrical Characteristics and Operating
4R, 5R, 6J
4R, 5R, 6J
Conditions for range.
1A, 1F, 1J,
1A, 1F, 1J,
VDDQ
Supply Isolated Output Buffer Supply: See DC Electrical Characteristics
1M, 1U, 7A,
1M, 1U, 7A,
and Operating Conditions for range.
7F, 7J, 7M,
7F, 7J, 7M,
7U
7U
(continued on next page)


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