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MT55L512L18P Datasheet(PDF) 13 Page - Micron Technology

Part No. MT55L512L18P
Description  8Mb ZBT SRAM
Download  30 Pages
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Maker  MICRON [Micron Technology]
Homepage  http://www.micron.com
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MT55L512L18P Datasheet(HTML) 13 Page - Micron Technology

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8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L512L18P_2.p65 – Rev. 6/01
©2001, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
BGA PIN DESCRIPTIONS
x 1 8
x32/x36
SYMBOL TYPE
DESCRIPTION
4P
4P
SA0
Input
Synchronous Address Inputs: These inputs are registered and
4N
4N
SA1
must meet the setup and hold times around the rising edge
2A, 3A, 5A,
2A, 2C, 2R,
S A
of CLK.
6A, 3B, 5B,
3A, 3B, 3C,
2C, 3C, 5C,
3T, 4T, 5A,
6C, 2R, 6R,
5B, 5C, 5T,
2T, 3T, 5T, 6T
6A, 6C, 6R
5 L
5 L
BWa#
Input
Synchronous Byte Write Enables: These active LOW inputs allow
3 G
5 G
BWb#
individual bytes to be written and must meet the setup and hold
3 G
BWc#
times around the rising edge of CLK. A byte write enable is LOW
3 L
BWd#
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQa’s and DQPa; BWb# controls DQb’s and DQPb.
For the x32 and x36 versions, BWa# controls DQa’s and DQPa;
BWb# controls DQb’s and DQPb; BWc# controls DQc’s and DQPc;
BWd# controls DQd’s and DQPd. Parity is only available on the x18
and x36 versions.
4 M
4 M
CKE#
Input
Synchronous Clock Enable: This active LOW input permits CLK to
propagate throughout the device. When CKE# is HIGH, the
device ignores the CK input and effectively internally extends
the previous CLK cycle. This input must meet the setup and
hold times around the rising edge of CLK.
4 H
4 H
R/W#
Input
Read/Write: This input determines the cycle type when ADV/
LD# is lOW and is the only means for determining READs and
WRITEs. READ cycles may not be converted into WRITEs (and
vice versa) other than by loading a new address. A LOW on this
pin permits BYTE WRITE operations must meet the setup and
hold times around the rising edge of CLK. Full bus-width
WRITEs occur if all byte write enables are LOW.
4K
4K
CLK
Input
Clock: This signal registers the address, data, chip enable, byte write
enables and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock’s rising
edge.
4E
4E
CE#
Input
Synchronous Chip Enable: This active LOW input is used to enable
the device. CE# is sampled only when a new external address is
loaded.
6 B
6 B
CE2#
Input
Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is
loaded.
7T
7T
ZZ
Input
Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored.
2 B
2 B
CE2
Input
Synchronous Chip Enable: This active HIGH input is used to enable
the device and is sampled only when a new external address is
loaded.
(continued on next page)


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