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MT55L512L18P Datasheet(PDF) 7 Page - Micron Technology

Part No. MT55L512L18P
Description  8Mb ZBT SRAM
Download  30 Pages
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Maker  MICRON [Micron Technology]
Homepage  http://www.micron.com
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MT55L512L18P Datasheet(HTML) 7 Page - Micron Technology

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7
8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L512L18P_2.p65 – Rev. 6/01
©2001, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
TQFP PIN DESCRIPTIONS (CONTINUED)
x18
x32/x36
SYMBOL TYPE
DESCRIPTION
88
88
R/W#
Input
Read/Write: This input determines the cycle type when
ADV/LD# is LOW and is the only means for determining
READs and WRITEs. READ cycles may not be converted into
WRITEs (and vice versa) other than by loading a new
address. A LOW on this pin permits BYTE WRITE operations
and must meet the setup and hold times around the rising
edge of CLK. Full bus-width WRITEs occur if all byte write
enables are LOW.
31
31
MODE
Input
Mode: This input selects the burst sequence. A LOW on
(LBO#)
this pin selects linear burst. NC or HIGH on this pin selects
interleaved burst. Do not alter input state while device is
operating. LBO# is the JEDEC-standard term for MODE.
(a) 58, 59, 62, 63,
(a) 52, 53, 56-59,
DQa
Input/
SRAM Data I/Os: Byte “a” is associated with DQa pins;
68, 69, 72-74
62, 63
Output
Byte “b” is associated with DQb pins; Byte “c” is
(b) 8, 9, 12, 13,
(b) 68, 69, 72-75,
DQb
associated with DQc pins; Byte “d” is associated with
18, 19, 22-24
78, 79
DQd pins. Input data must meet setup and hold times
(c) 2, 3, 6-9,
DQc
around the rising edge of CLK.
12, 13
(d) 18, 19, 22-25,
DQd
28, 29
n/a
51
NF/DQPa
NF/
No Function/Data Bits: On the x32 version, these pins are
80
NF/DQPb
I/O
No Function (NF) and can be left floating or connected to
1
NF/DQPc
GND to minimize thermal impedance. On the x36 version,
30
NF/DQPd
these bits are DQPs.
14, 15, 16, 41, 65,
14, 15, 16, 41, 65,
VDD
Supply
Power Supply: See DC Electrical Characteristics and
66, 91
66, 91
Operating Conditions for range.
4, 11, 20, 27,
4, 11, 20, 27,
VDDQ
Supply
Isolated Output Buffer Supply: See DC Electrical
54, 61, 70, 77
54, 61, 70, 77
Characteristics and Operating Conditions for range.
5, 10, 17, 21,
5, 10, 17, 21,
VSS
Supply
Ground: GND.
26, 40, 55, 60,
26, 40, 55, 60,
67, 71, 76, 90
67, 71, 76, 90
1-3, 6, 7, 25,
n/a
NC
No Connect: These pins can be left floating or connected
28-30, 51-53, 56,
to GND to minimize thermal impedance.
57, 75, 78, 79,
95, 96
38, 39, 42, 43
38, 39, 42, 43
DNU
Do Not Use: These signals may either be unconnected or
wired to GND to minimize thermal impedance.
84
84
NF
No Function: This pin is internally connected to the die and
will have the capacitance of an input pin. It is allowable to
leave this pin unconnected or driven by signals. Pin 84 is
reserved as an address pin for the 18Mb ZBT SRAM.


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