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MT48LC8M16A2TG-7E Datasheet(PDF) 17 Page - Micron Technology |
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MT48LC8M16A2TG-7E Datasheet(HTML) 17 Page - Micron Technology |
17 / 59 page 17 128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MSDRAM_E.p65 – Rev. E; Pub. 1/02 ©2001, Micron Technology, Inc. 128Mb: x4, x8, x16 SDRAM This is shown in Figure 7 for CAS latencies of two and three; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. The 128Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architec- Figure 7 Consecutive READ Bursts ture. A READ command can be initiated on any clock cycle following a previous READ command. Full-speed random read accesses can be performed to the same bank, as shown in Figure 8, or each subsequent READ may be performed to a different bank. NOTE: Each READ command may be to any bank. DQM is LOW. CLK DQ DOUT n T2 T1 T4 T3 T6 T5 T0 COMMAND ADDRESS READ NOP NOP NOP NOP BANK, COL n NOP BANK, COL b DOUT n + 1 DOUT n + 2 DOUT n + 3 DOUT b READ X = 1 cycle CAS Latency = 2 CLK DQ DOUT n T2 T1 T4 T3 T6 T5 T0 COMMAND ADDRESS READ NOP NOP NOP NOP BANK, COL n NOP BANK, COL b DOUT n + 1 DOUT n + 2 DOUT n + 3 DOUT b READ NOP T7 X = 2 cycles CAS Latency = 3 DON’T CARE |
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