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MT48LC8M16A2FC-75 Datasheet(PDF) 52 Page - Micron Technology |
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MT48LC8M16A2FC-75 Datasheet(HTML) 52 Page - Micron Technology |
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52 / 59 page  52 128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MSDRAM_E.p65 – Rev. E; Pub. 1/02 ©2001, Micron Technology, Inc. 128Mb: x4, x8, x16 SDRAM NOTE: 1. For this example, the burst length = 1. 2. x16: A9 and A11 = “Don’t Care” x8: A11 = “Don’t Care” 3. WRITE command not allowed else tRAS would be violated. ENABLE AUTO PRECHARGE tCH tCL tCK tRP tRAS tRCD tRC DQM / DQML, DQMH CKE CLK A0-A9, A11 DQ BA0, BA1 A10 tCMH tCMS tAH tAS ROW ROW BANK BANK ROW ROW BANK tWR DIN m COMMAND tCMH tCMS NOP3 NOP3 NOP ACTIVE NOP3 WRITE NOP ACTIVE tAH tAS tAH tAS tDH tDS tCKH tCKS NOP NOP COLUMN m 2 T0 T1 T2 T4 T3 T5 T6 T7 T8 T9 DON’T CARE SINGLE WRITE – WITH AUTO PRECHARGE 1 *CAS latency indicated in parentheses. -7E -75 -8E SYMBOL* MIN MAX MIN MAX MIN MAX UNITS tCMS 1.5 1.5 2 ns tDH 0.8 0.8 1 ns tDS 1.5 1.5 2 ns tRAS 37 120,000 44 120,000 50 120,000 ns tRC 60 66 70 ns tRCD 15 20 20 ns tRP 15 20 20 ns tWR 1 CLK + 1 CLK + 1 CLK + – 7ns 7.5ns 7ns TIMING PARAMETERS -7E -75 -8E SYMBOL* MIN MAX MIN MAX MIN MAX UNITS tAH 0.8 0.8 1 ns tAS 1.5 1.5 2 ns tCH 2.5 2.5 3 ns tCL 2.5 2.5 3 ns tCK (3) 7 7.5 8 ns tCK (2) 7.5 10 10 ns tCKH 0.8 0.8 1 ns tCKS 1.5 1.5 2 ns tCMH 0.8 0.8 1 ns |
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