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MT48LC8M16A2FB-75 Datasheet(PDF) 44 Page - Micron Technology |
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MT48LC8M16A2FB-75 Datasheet(HTML) 44 Page - Micron Technology |
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44 / 59 page  44 128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MSDRAM_E.p65 – Rev. E; Pub. 1/02 ©2001, Micron Technology, Inc. 128Mb: x4, x8, x16 SDRAM NOTE: 1. For this example, the burst length = 1, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE. 2. x16: A9 and A11 = “Don’t Care” x8: A11 = “Don’t Care” 3. PRECHARGE command not allowed or tRAS would be violated. *CAS latency indicated in parentheses. -7E -75 -8E SYMBOL* MIN MAX MIN MAX MIN MAX UNITS tCMH 0.8 0.8 1 ns tCMS 1.5 1.5 2 ns tHZ(3) 5.4 5.4 6 ns tHZ(2) 5.4 6 6 ns tLZ 111 ns tOH 333 ns tRAS 37 120,000 44 120,000 50 120,000 ns tRC 60 66 70 ns tRCD 15 20 20 ns tRP 15 20 20 ns TIMING PARAMETERS -7E -75 -8E SYMBOL* MIN MAX MIN MAX MIN MAX UNITS tAC (3) 5.4 5.4 6 ns tAC (2) 5.4 6 6 ns tAH 0.8 0.8 1 ns tAS 1.5 1.5 2 ns tCH 2.5 2.5 3 ns tCL 2.5 2.5 3 ns tCK (3) 7 7.5 8 ns tCK (2) 7.5 10 10 ns tCKH 0.8 0.8 1 ns tCKS 1.5 1.5 2 ns SINGLE READ – WITHOUT AUTO PRECHARGE 1 ALL BANKS tCH tCL tCK tAC tLZ tRP tRAS tRCD CAS Latency tRC tOH DOUT m tCMH tCMS tAH tAS tAH tAS tAH tAS ROW ROW BANK BANK(S) BANK ROW ROW BANK tHZ tCMH tCMS NOP NOP NOP PRECHARGE ACTIVE NOP READ ACTIVE NOP DISABLE AUTO PRECHARGE SINGLE BANKS DON’T CARE UNDEFINED COLUMN m2 tCKH tCKS T0 T1 T2 T3 T4 T5 T6 T7 T8 DQM / DQML, DQMH CKE CLK A0-A9, A11 DQ BA0, BA1 A10 COMMAND 3 3 |
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