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MT48LC8M16A2FB-75 Datasheet(PDF) 8 Page - Micron Technology |
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MT48LC8M16A2FB-75 Datasheet(HTML) 8 Page - Micron Technology |
8 / 59 page 8 128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MSDRAM_E.p65 – Rev. E; Pub. 1/02 ©2001, Micron Technology, Inc. 128Mb: x4, x8, x16 SDRAM PIN DESCRIPTIONS TSOP PIN NUMBERS SYMBOL TYPE DESCRIPTION 38 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. 37 CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power- down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH. 19 CS# Input Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is regis- tered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. 16, 17, 18 WE#, CAS#, Input Command Inputs: WE#, CAS#, and RAS# (along with CS#) define the RAS# command being entered. 39 x4, x8: DQM Input Input/Output Mask: DQM is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when 15, 39 x16: DQML, DQM is sampled HIGH during a WRITE cycle. The output buffers are DQMH placed in a High-Z state (two-clock latency) when DQM is sampled HIGH during a READ cycle. On the x4 and x8, DQML (Pin 15) is a NC and DQMH is DQM. On the x16, DQML corresponds to DQ0-DQ7 and DQMH corresponds to DQ8-DQ15. DQML and DQMH are considered same state when referenced as DQM. 20, 21 BA0, BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank the ACTIVE, READ, WRITE, or PRECHARGE command is being applied. 23-26, 29-34, 22, 35 A0-A11 Input Address Inputs: A0-A11 are sampled during the ACTIVE command (row- address A0-A11) and READ/WRITE command (column-address A0-A9, A11 [x4]; A0-A9 [x8]; A0-A8 [x16]; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 [HIGH]) or bank selected by BA0, BA1 (A10 [LOW]). The address inputs also provide the op-code during a LOAD MODE REGISTER command. 2, 4, 5, 7, 8, 10, 11, 13, 42, DQ0-DQ15 x16: I/O Data Input/Output: Data bus for x16 (4, 7, 10, 13, 42, 45, 48, and 51 are 44, 45, 47, 48, 50, 51, 53 NCs for x8; and 2, 4, 7, 8, 10, 13, 42, 45, 47, 48, 51, and 53 are NCs for x4). 2, 5, 8, 11, 44, 47, 50, 53 DQ0-DQ7 x8: I/O Data Input/Output: Data bus for x8 (2, 8, 47, 53 are NCs for x4). 5, 11, 44, 50 DQ0-DQ3 x4: I/O Data Input/Output: Data bus for x4. 40 NC – No Connect: These pins should be left unconnected. 36 NC – Address input (A12) for the 256Mb and 512Mb devices 3, 9, 43, 49 VDDQ Supply DQ Power: Isolated DQ power on the die for improved noise immunity. 6, 12, 46, 52 VSSQ Supply DQ Ground: Isolated DQ ground on the die for improved noise immunity. 1, 14, 27 VDD Supply Power Supply: +3.3V ±0.3V. 28, 41, 54 VSS Supply Ground. |
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