13

1 Meg x 16 FPM DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D51_5V_B.p65 – Rev. B; Pub 3/01

©2001, Micron Technology, Inc.

1 MEG x 16

FPM DRAM

VALID D

OUT

VALID D

IN

ROW

COLUMN

ROW

V

V

IH

IL

V

V

IH

IL

ADDR

V

V

IH

IL

V

V

IH

IL

DQ

V

V

IOH

IOL

V

V

IH

IL

RAS#

OPEN

OPEN

tOE

tOD

tCAC

tRAC

tAA

tCLZ

tDS

tDH

tAWD

tWP

tRWL

tCWL

tCWD

tRWD

tRCS

tASC

tCAH

tAR

tASR

tRAD

tCRP

tRCD

tCAS

tRSH

tCSH

tRAS

tRWC

tRP

tRAH

OE#

tOEH

tCLCH

WE#

CASL#/CASH#

DON’T CARE

UNDEFINED

READ-WRITE CYCLE

(LATE WRITE and READ-MODIFY-WRITE cycles)

TIMING PARAMETERS

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

25

30

ns

38

45

ns

0

0

ns

0

0

ns

42

49

ns

15

15

ns

8

10

ns

8

10,000

10

10,000

ns

10

10

ns

0

0

ns

5

5

ns

38

45

ns

28

35

ns

8

10

ns

8

10

ns

0

0

ns

0

12

0

15

ns

12

15

ns

8

10

ns

50

60

ns

9

12

ns

9

10

ns

50

10,000

60

10,000

ns

11

14

ns

0

0

ns

30

40

ns

13

15

ns

116

140

ns

67

79

ns

13

15

ns

5

5

ns

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS