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MT48LC8M16A2FC-8E Datasheet(PDF) 20 Page - Micron Technology |
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MT48LC8M16A2FC-8E Datasheet(HTML) 20 Page - Micron Technology |
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20 / 59 page  20 128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MSDRAM_E.p65 – Rev. E; Pub. 1/02 ©2001, Micron Technology, Inc. 128Mb: x4, x8, x16 SDRAM Figure 11 READ to PRECHARGE A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full-page burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 11 for each possible CAS latency; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data element(s). In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the opti- mum time (as described above) provides the same op- eration that would result from the same fixed-length burst with auto precharge. The disadvantage of the DON’T CARE CLK DQ DOUT n T2 T1 T4 T3 T6 T5 T0 COMMAND ADDRESS READ NOP NOP NOP NOP NOP DOUT n + 1 DOUT n + 2 DOUT n + 3 PRECHARGE ACTIVE t RP T7 NOTE: DQM is LOW. CLK DQ DOUT n T2 T1 T4 T3 T6 T5 T0 COMMAND ADDRESS READ NOP NOP NOP NOP NOP DOUT n + 1 DOUT n + 2 DOUT n + 3 PRECHARGE ACTIVE t RP T7 X = 1 cycle CAS Latency = 2 CAS Latency = 3 X = 2 cycles BANK a, COL n BANK a, ROW BANK (a or all) BANK a, COL n BANK a, ROW BANK (a or all) |
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