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MT48LC8M16A2FC-8E Datasheet(PDF) 19 Page - Micron Technology |
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MT48LC8M16A2FC-8E Datasheet(HTML) 19 Page - Micron Technology |
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19 / 59 page  19 128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MSDRAM_E.p65 – Rev. E; Pub. 1/02 ©2001, Micron Technology, Inc. 128Mb: x4, x8, x16 SDRAM Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed- length READ burst may be immediately followed by data from a WRITE command (subject to bus turnaround limitations). The WRITE burst may be initiated on the clock edge immediately following the last (or last de- sired) data element from the READ burst, provided that I/ O contention can be avoided. In a given system design, there may be a possibility that the device driving the input data will go Low-Z before the SDRAM DQs go High- Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command. The DQM input is used to avoid I/O contention, as shown in Figures 9 and 10. The DQM signal must be asserted (HIGH) at least two clocks prior to the WRITE command (DQM latency is two clocks for output buffers) DON’T CARE READ NOP NOP NOP NOP DQM CLK DQ DOUT n T2 T1 T4 T3 T0 COMMAND ADDRESS BANK, COL n WRITE DIN b BANK, COL b T5 DS tHZ t NOTE: A CAS latency of three is used for illustration. The READ command may be to any bank, and the WRITE command may be to any bank. Figure 10 READ to WRITE With Extra Clock Cycle Figure 9 READ to WRITE READ NOP NOP WRITE NOP CLK T2 T1 T4 T3 T0 DQM DQ DOUT n COMMAND DIN b ADDRESS BANK, COL n BANK, COL b DS tHZ t tCK NOTE: A CAS latency of three is used for illustration. The READ command may be to any bank, and the WRITE command may be to any bank. If a burst of one is used, then DQM is not required. to suppress data-out from the READ. Once the WRITE command is registered, the DQs will go High-Z (or re- main High-Z), regardless of the state of the DQM signal, provided the DQM was active on the clock just prior to the WRITE command that truncated the READ com- mand. If not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during T4 in Figure 10, then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid. The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Figure 9 shows the case where the clock frequency allows for bus contention to be avoided without adding a NOP cycle, and Figure 10 shows the case where the additional NOP is needed. |
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