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MT4C1M16E5 Datasheet(PDF) 1 Page - Micron Technology

Part No. MT4C1M16E5
Description  EDO DRAM
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Manufacturer  MICRON [Micron Technology]
Direct Link  http://www.micron.com
Logo MICRON - Micron Technology

MT4C1M16E5 Datasheet(HTML) 1 Page - Micron Technology

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1
1 Meg x 16 EDO DRAM
D52_B.p65 – Rev. B; Pub. 3/01
©2001, Micron Technology, Inc
16Mb: 1 MEG x16
EDO DRAM
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
KEY TIMING PARAMETERS
SPEED
tRC
tRAC
tPC
tAA
tCAC
tCAS
-5
84ns
50ns
20ns
25ns
15ns
8ns
-6
104ns
60ns
25ns
30ns
17ns
10ns
FEATURES
• JEDEC- and industry-standard x16 timing,
functions, pinouts, and packages
• High-performance CMOS silicon-gate process
• Single power supply (+3.3V ±0.3V or 5V ±10%)
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#
(CBR), HIDDEN; optional self refresh (S)
• BYTE WRITE access cycles
• 1,024-cycle refresh (10 row, 10 column addresses)
• Extended Data-Out (EDO) PAGE MODE access
• 5V-tolerant inputs and I/Os on 3.3V devices
OPTIONS
MARKING
• Voltages1
3.3V
LC
5V
C
• Refresh Addressing
1,024 (1K) rows
E5
• Packages
Plastic SOJ (400 mil)
DJ
Plastic TSOP (400 mil)
TG
• Timing
50ns access
-5
60ns access
-6
• Refresh Rates
Standard Refresh (16ms period)
None
Self Refresh (128ms period)
S2
• Operating Temperature Range
Commercial (0oC to +70oC)
None
Extended (-20oC to +80oC)
ET
Part Number Example:
MT4LC1M16E5TG-6
NOTE: 1. The third field distinguishes the low voltage offering: LC desig-
nates Vcc = 3.3V and C designates Vcc = 5V.
2. Available only on MT4LC1M16E5 (3.3V)
PIN ASSIGNMENT (Top View)
44/50-Pin TSOP
42-Pin SOJ
1 MEG x 16 EDO DRAM PART NUMBERS
PART NUMBER
Vcc REFRESH PACKAGE REFRESH
MT4LC1M16E5DJ-x
3.3V
1K
400-SOJ
Standard
MT4LC1M16E5DJ-x S
3.3V
1K
400-SOJ
Self
MT4LC1M16E5TG-x
3.3V
1K
400-TSOP
Standard
MT4LC1M16E5TG-x S
3.3V
1K
400-TSOP
Self
MT4C1M16E5DJ-x
5V
1K
400-SOJ
Standard
MT4C1M16E5TG-x
5V
1K
400-TSOP
Standard
NOTE: “-x” indicates speed grade marking under timing
options.
EDO DRAM
MT4C1M16E5 – 1 Meg x 16, 5V
MT4LC1M16E5 – 1 Meg x 16, 3.3V
For the latest data sheet, please refer to the Micron Web
site: www.micron.com/products/datasheets/sdramds.html
NOTE: The "#" symbol indicates signal is active LOW.
VCC
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
NC
NC
NC
WE#
RAS#
NC
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
36
35
34
33
32
31
30
29
28
27
26
VSS
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
NC
NC
CASL#
CASH#
OE#
A9
A8
A7
A6
A5
A4
VSS
VCC
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
NC
NC
WE#
RAS#
NC
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
VSS
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
NC
CASL#
CASH#
OE#
A9
A8
A7
A6
A5
A4
VSS
GENERAL DESCRIPTION
The 1 Meg x 16 is a randomly accessed, solid-state
memory containing 16,777,216 bits organized in a x16
configuration. The 1 Meg x 16 has both BYTE WRITE
and WORD WRITE access cycles via two CAS# pins
(CASL# and CASH#). These function like a single CAS#
found on other DRAMs in that either CASL# or CASH#
will generate an internal CAS#.
The CAS# function and timing are determined by
the first CAS# (CASL# or CASH#) to transition LOW and
the last CAS# to transition back HIGH. Using only one


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