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MT48LC8M16A2TG-6A Datasheet(PDF) 1 Page - Micron Technology

Part No. MT48LC8M16A2TG-6A
Description  SYNCHRONOUS DRAM
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Manufacturer  MICRON [Micron Technology]
Direct Link  http://www.micron.com
Logo MICRON - Micron Technology

MT48LC8M16A2TG-6A Datasheet(HTML) 1 Page - Micron Technology

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PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
x16 Addendum
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT48lc8m16a2_addendum.fm - Rev. 7/02
1
©2002, Micron Technology Inc.
128Mb x16
SDRAM Addendum
PRELIMINARY
SYNCHRONOUS
DRAM
MT48LC8M16A2 – 2 MEG X 16 X 4 BANKS
For the latest data sheet, please refer to the Micron Web
site: www.micron.com/dramds
FEATURES
• Supports PC100 and PC133 functionality
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
• Self Refresh Mode; standard and low power
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
• 64ms, 4,096-cycle refresh
Part Number:
MT48LC8M16A2TG-6A
ADDENDUM CHANGES
The standard 128Mb SDRAM data sheets also per-
tain to the x16 device and should be referenced for a
complete description of SDRAM functionality and
operating modes. However, to meet the faster speed
grades, some of the AC timing parameters are slightly
different. This addendum data sheet will concentrate
on the key differences required to support the
enhanced speeds.
The Micron 128Mb data sheet provides full specifi-
cations and functionality unless specified herein.
OPTION
MARKING
• Configuration
8 Meg x 16 (2 Meg x 16 x 4 banks)
8M16
WRITE Recovery (tWR)
tWR = “2 CLK”1
NOTE:
1. Refer to Micron Technical Note: TN-48-05.
A2
•Package
Plastic Package – OCPL2
2. Off-center parting line.
54-pin TSOP II (400 mil)
TG
• Timing (Cycle Time)
6.0ns @ CL = 3
-6A
• Self Refresh
Standard
None
•Operating Temperature Range
Commercial (0oC to +70oC)
None
8 MEG X 16
Configuration
2 Meg x 16 x 4 banks
Refresh Count
4K
Row Addressing
4K (A0–A11)
Bank Addressing
4 (BA0, BA1)
Column Addressing
512 (A0–A8)
KEY TIMING PARAMETERS
SPEED
GRADE
CLOCK
FREQUENCY
ACCESS
TIME
CL = 3*
SETUP
TIME
HOLD
TIME
-6A
167 MHz
5.4ns
1.5ns
0.8ns


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