MT46V32M16TG-8L datasheet(58/68 Pages) MICRON

Part #	MT46V32M16TG-8L

Description	DOUBLE DATA RATE DDR SDRAM

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Manufacturer	MICRON [Micron Technology]

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58

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mx4x8x16DDR_B.p65 – Rev. B; Pub 4/01

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

Figure 31

Data Input Timing

Figure 30

Data Output Timing - tAC and tDQSCK

CK

CK#

DQS, or LDQS/UDQS2

T07

T1

T2

T3

T4

T5

T2n

T3n

T4n

T5n

T6

NOTE: 1. tDQSCK is the DQS output window relative to CK and is the“long term” component of DQS skew.

2. DQs transitioning after DQS transition define tDQSQ window.

3. All DQs must transition by tDQSQ after DQS transitions, regardless of tAC.

4. tAC is the DQ output window relative to CK, and is the“long term” component of DQ skew.

5. tLZ(MIN) and tAC(MIN) are the first valid signal transition.

6. tHZ(MAX ,and tAC(MAX) are the latest valid signal transition.

7. READ command with CL = 2 issued at T0.

tRPST

tLZ(MIN)

tDQSCK1(MAX)

tDQSCK1(MIN)

tDQSCK1(MAX)

tDQSCK1(MIN)

tHZ(MAX)

tRPRE

DQ (Last data valid)

DQ (First data valid)

All DQs collectively3

tAC4(MIN)

tAC4(MAX)

tLZ(MIN)

tHZ(MAX)

T2

T2n

T3n

T4n

T5n

T2n

T3n

T4n

T5n

T3

T4

T5

T2

T3

T4

T5

T3

DQS

tDQSS

tDQSH tWPST

tDH

tDS

tDQSL

tDSS2 tDSH1

tDSH1

tDSS2

DM

DQ

CK

CK#

T03

T1

T1n

T2

T2n

T3

DI

b

NOTE: 1. tDSH(MIN) generally occurs during tDQSS(MIN).

2. tDSS(MIN) generally occurs during tDQSS(MAX).

3. WRITE command issued at T0.

4. For x16, LDQS controls the lower byte and UDQS controls the upper byte.

DON’T CARE

TRANSITIONING DATA

tWPRE

tWPRES

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MT46V32M16TG-8L Datasheet(PDF) 58 Page - Micron Technology

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