MT48LC2M32B2 datasheet(35/53 Pages) MICRON

Part #	MT48LC2M32B2

Description	SYNCHRONOUS DRAM

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Manufacturer	MICRON [Micron Technology]

Direct Link	http://www.micron.com

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35

64Mb: x32 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02

64Mb: x32

SDRAM

13. IDD specifications are tested after the device is prop-

erly initialized.

14. Timing actually specified by tCKS; clock(s) speci-

fied as a reference only at minimum cycle rate.

15. Timing actually specified by tWR plus tRP; clock(s)

specified as a reference only at minimum cycle rate.

16. Timing actually specified by tWR.

17. Required clocks are specified by JEDEC function-

ality and are not dependent on any timing param-

eter.

18. The IDD current will decrease as the CAS latency is

reduced. This is due to the fact that the maximum

cycle rate is slower as the CAS latency is reduced.

19. Address transitions average one transition every

two clocks.

20. CLK must be toggled a minimum of two times dur-

ing this period.

21. Based on tCK = 143 MHz for -7, 166 MHz for -6,

183 MHz for -55, and 200 MHz for -5.

22. VIH overshoot: VIH(MAX) = VDDQ + 1.2V for a pulse

width

≤ 3ns, and the pulse width cannot be greater

than one third of the cycle rate. VIL undershoot:

VIL(MIN) = -1.2V for a pulse width

≤ 3ns, and the

pulse width cannot be greater than one third of the

cycle rate.

23. The clock frequency must remain constant during

access or precharge states (READ, WRITE, includ-

ing tWR, and PRECHARGE commands). CKE may

be used to reduce the data rate.

24. Auto precharge mode only.

25. JEDEC and PC100 specify three clocks.

26. tCK = 7ns for -7, 6ns for -6, 5.5ns for -5.5, and

5ns for -5.

27. VDD(MIN) = 3.135V for -6, -55, and -5 speed grades.

28. Check factory for availability of specially screened

devices having tWR = 10ns. tWR = 1 tCK for 100 MHz

and slower (tCK = 10ns and higher) in manual

precharge.

NOTES

1.

All voltages referenced to VSS.

2.

This parameter is sampled. VDD, VDDQ = +3.3V;

f = 1 MHz, TA = 25°C; pin under test biased at 1.4V.

AC can range from 0pF to 6pF.

3.

IDD is dependent on output loading and cycle rates.

Specified values are obtained with minimum cycle

time and the outputs open.

4.

Enables on-chip refresh and address counters.

5.

The minimum specifications are used only to indi-

cate cycle time at which proper operation over the

full temperature range (0°C

≤ T

A ≤

+70°C and

-40°C

≤ T

A ≤

+85°C for IT parts) is ensured.

6.

An initial pause of 100µs is required after power-

up, followed by two AUTO REFRESH commands,

before proper device operation is ensured. (VDD

and VDDQ must be powered up simultaneously. VSS

and VSSQ must be at same potential.) The two

AUTO REFRESH command wake-ups should be

repeated any time the tREF refresh requirement is

exceeded.

7.

AC characteristics assume tT = 1ns.

8.

In addition to meeting the transition rate specifi-

cation, the clock and CKE must transit between VIH

and VIL (or between VIL and VIH) in a monotonic

manner.

9.

Outputs measured at 1.5V with equivalent load:

10. tHZ defines the time at which the output achieves

the open circuit condition; it is not a reference to

VOH or VOL. The last valid data element will meet

tOH before going High-Z.

11. AC timing and IDD tests have VIL = .25 and VIH = 2.75,

with timing referenced to 1.5V crossover point.

12. Other input signals are allowed to transition no

more than once in any two-clock period and are

otherwise at valid VIH or VIL levels.

Q

30pF

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