Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

MT48LC1M16A1S Datasheet(PDF) 5 Page - Micron Technology

Part No. MT48LC1M16A1S
Description  SYNCHRONOUS DRAM
Download  51 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  MICRON [Micron Technology]
Direct Link  http://www.micron.com
Logo MICRON - Micron Technology

MT48LC1M16A1S Datasheet(HTML) 5 Page - Micron Technology

  MT48LC1M16A1S Datasheet HTML 1Page - Micron Technology MT48LC1M16A1S Datasheet HTML 2Page - Micron Technology MT48LC1M16A1S Datasheet HTML 3Page - Micron Technology MT48LC1M16A1S Datasheet HTML 4Page - Micron Technology MT48LC1M16A1S Datasheet HTML 5Page - Micron Technology MT48LC1M16A1S Datasheet HTML 6Page - Micron Technology MT48LC1M16A1S Datasheet HTML 7Page - Micron Technology MT48LC1M16A1S Datasheet HTML 8Page - Micron Technology MT48LC1M16A1S Datasheet HTML 9Page - Micron Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 5 / 51 page
background image
16Mb: x16 SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
16MSDRAMx16.p65 – Rev. 8/99
©1999, Micron Technology, Inc.
5
16Mb: x16
SDRAM
PIN DESCRIPTIONS
PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
35
CLK
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal
burst counter and controls the output registers.
34
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK
signal. Deactivating the clock provides PRECHARGE POWER-DOWN
and SELF REFRESH operations (all banks idle), ACTIVE POWER-DOWN
(row ACTIVE in either bank) or CLOCK SUSPEND operation (burst/access
in progress). CKE is synchronous except after the device enters power-
down and self refresh modes, where CKE becomes asynchronous until
after exiting the same mode. The input buffers, including CLK, are
disabled during power-down and self refresh modes, providing low
standby power. CKE may be tied HIGH.
18
CS#
Input
Chip Select: CS# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS# is
registered HIGH. CS# provides for external bank selection on systems
with multiple banks. CS# is considered part of the command code.
15, 16, 17
WE#, CAS#,
Input
Command Inputs: RAS#, CAS# and WE# (along with CS#) define the
RAS#
command being entered.
14, 36
DQML,
Input
Input/Output Mask: DQM is an input mask signal for write accesses and an
DQMH
output enable signal for read accesses. Input data is masked when
DQM is sampled HIGH during a WRITE cycle. The output buffers are
placed in a High-Z state (two-clock latency) when DQM is sampled
HIGH during a READ cycle. DQML corresponds to DQ0-DQ7; DQMH
corresponds to DQ8-DQ15.
DQML and DQMH are considered same state when referenced as DQM.
19
BA
Input
Bank Address Inputs: BA defines to which bank the ACTIVE, READ,
WRITE or PRECHARGE command is being applied. BA is also used to
program the twelfth bit of the Mode Register.
21-24, 27-32, 20
A0-A10
Input
Address Inputs: A0-A10 are sampled during the ACTIVE command
(row-address A0-A10) and READ/WRITE command (column-address A0-
A7, with A10 defining AUTO PRECHARGE) to select one location out of
the 512K available in the respective bank. A10 is sampled during a
PRECHARGE command to determine if all banks are to be precharged
(A10 HIGH). The address inputs also provide the op-code during a
LOAD MODE REGISTER command.
2, 3, 5, 6, 8, 9,
DQ0-
Input/ Data I/Os: Data bus.
11, 12, 39, 40, 42,
DQ15
Output
43, 45, 46, 48, 49
33, 37
NC
No Connect: These pins should be left unconnected.
7, 13, 38, 44
VDDQ
Supply DQ Power: Provide isolated power to DQs for improved noise immu-
nity.
4, 10, 41, 47
VSSQ
Supply DQ Ground: Provide isolated ground to DQs for improved noise
immunity.
1, 25
VDD
Supply Power Supply: +3.3V ±0.3V.
26, 50
VSS
Supply Ground.


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51 


Datasheet Download

Go To PDF Page

Related Electronics Part Number

Part No.DescriptionHtml ViewManufacturer
M5M4V64S30ATP-8A 64M 4-BANK x 2097152-WORD x 8-BIT Synchronous DRAM 1  2  3  4  5  More Mitsubishi Electric Semiconductor
MH64D64AKQH-75 4 294 967 296-BIT 67 108 864-WORD BY 64-BIT Double Data Rate Synchronous DRAM Module 1  2  3  4  5  More Mitsubishi Electric Semiconductor
K4S281632B-N 2M x 16Bit x 4 Banks Synchronous DRAM in sTSOP 1  2  3  4  5  More Samsung semiconductor
HYB39S16400 16 MBit Synchronous DRAM 1  2  3  4  5  More Siemens Semiconductor Group
HC2509C Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications 1  2  3  4  5  More Hynix Semiconductor
MT48LC2M32B2 SYNCHRONOUS DRAM 1  2  3  4  5  More Micron Technology
GLT5640L32 CMOS Synchronous DRAM 2M x 32 SDRAM 1  2  3  4  5  More List of Unclassifed Manufacturers
HY57V161610E 2 Banks x 512K x 16 Bit Synchronous DRAM 1  2  3  4  5  More Hynix Semiconductor
A43L1616 1M X 16 Bit X 2 Banks Synchronous DRAM 1  2  3  4  5  More AMIC Technology
UPD45128163-A75L 128M-bit Synchronous DRAM 4-bank LVTTL 1  2  3  4  5  More Elpida Memory

Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn