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MT46V32M16TG-75L Datasheet(PDF) 1 Page - Micron Technology |
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MT46V32M16TG-75L Datasheet(HTML) 1 Page - Micron Technology |
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1 / 68 page  1 512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512Mx4x8x16DDR_B.p65 – Rev. B; Pub 4/01 ©2001, Micron Technology, Inc. 512Mb: x4, x8, x16 DDR SDRAM ADVANCE‡ ‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS. DOUBLE DATA RATE (DDR) SDRAM MT46V128M4 – 32 Meg x 4 x 4 banks MT46V64M8 – 16 Meg x 8 x 4 banks MT46V32M16 – 8 Meg x 16 x 4 banks For the latest data sheet revisions, please refer to the Micron Web site:www.micron.com/datasheets PIN ASSIGNMENT (TOP VIEW) 66-Pin TSOP FEATURES •VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V • Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (x16 has two – one per byte) • Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle • Differential clock inputs (CK and CK#) • Commands entered on each positive CK edge • DQS edge-aligned with data for READs; center- aligned with data for WRITEs • DLL to align DQ and DQS transitions with CK • Four internal banks for concurrent operation • Data mask (DM) for masking write data (x16 has two – one per byte) • Programmable burst lengths: 2, 4, or 8 • x16 has programmable IOL/IOV. • Concurrent auto precharge option is supported • Auto Refresh and Self Refresh Modes • Longer lead TSOP for improved reliability (OCPL) • 2.5V I/O (SSTL_2 compatible) OPTIONS MARKING • Configuration 128 Meg x 4 (32 Meg x 4 x 4 banks) 128M4 64 Meg x 8 (16 Meg x 8 x 4 banks) 64M8 32 Meg x 16 (8 Meg x 16 x 4 banks) 32M16 • Plastic Package – OCPL 66-pin TSOP (standard 22.3mm length) TG (400 mil width, 0.65mm pin pitch) • Timing – Cycle Time 7.5ns @ CL = 2 (DDR266B)1 -75Z 7.5ns @ CL = 2.5 (DDR266B)2 -75 10ns @ CL = 2 (DDR200)2 -8 • Self Refresh Standard none Low Power L NOTE: 1. Supports PC2100 modules with 2-3-3 timing 2. Supports PC2100 modules with 2.5-3-3 timing 3. Supports PC1600 modules with 2-2-2 timing 128 Meg x 4 64 Meg x 8 32 Meg x 16 Configuration 32 Meg x 4 x 4 banks 16 Meg x 8 x 4 banks 8 Meg x 16 x 4 banks RefreshCount 8K 8K 8K RowAddressing 8K(A0–A12) 8K(A0–A12) 8K(A0–A12) BankAddressing 4(BA0,BA1) 4(BA0,BA1) 4(BA0,BA1) ColumnAddressing 4K(A0–A9,A11,A12) 2K(A0–A9, A11) 1K(A0–A9) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS DNU VREF VSS UDM CK# CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS x16 VDD DQ0 VDDQ DQ1 DQ2 VssQ DQ3 DQ4 VDDQ DQ5 DQ6 VssQ DQ7 NC VDD Q LDQS NC VDD DNU LDM WE# CAS# RAS# CS# NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD x16 VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC VSSQ DQS DNU VREF VSS DM CK# CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS x8 x4 VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC NC VSSQ DQS DNU VREF VSS DM CK# CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD DNU NC WE# CAS# RAS# CS# NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD x8 x4 VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC NC VDDQ NC NC VDD DNU NC WE# CAS# RAS# CS# NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD KEY TIMING PARAMETERS SPEED CLOCK RATE DATA-OUT ACCESS DQS-DQ GRADE CL = 2** CL = 2.5** WINDOW* WINDOW SKEW -75 133 MHz 133 MHz 2.5ns ±0.75ns +0.5ns -75 100 MHz 133 MHz 2.5ns ±0.75ns +0.5ns -8 100 MHz 125 MHz 3.4ns ±0.8ns +0.6ns *Minimum clock rate @ CL = 2 (-8) and CL = 2.5 (-75) **CL = CAS (Read) Latency |
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