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ML4851 Datasheet(PDF) 5 Page - Micro Linear Corporation |
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ML4851 Datasheet(HTML) 5 Page - Micro Linear Corporation |
5 / 9 page 5 ML4851 July 2000 DATASHEET FUNCTIONAL DESCRIPTION The ML4851 combines Pulse Frequency Modulation (PFM) and synchronous rectification to create a boost converter that is both highly efficient and simple to use. A PFM regulator charges a single inductor for a fixed period of time and then completely discharges before another cycle begins, simplifying the design by eliminating the need for conventional current limiting circuitry. Synchronous rectification is accomplished by replacing an external Schottky diode with an on-chip PMOS device, reducing switching losses and external component count. REGULATOR OPERATION A block diagram of the boost converter is shown in Figure 2. The circuit remains idle when VOUT is at or above the desired output voltage, drawing 50µA from VIN, and 8µA from VOUT through the feedback resistors R1 and R2. When VOUT drops below the desired output level, the output of amplifier A1 goes high, signaling the regulator to deliver charge to the output. Since the output of amplifier A2 is normally high, the flip-flop captures the A1 set signal and creates a pulse at the gate of the NMOS transistor Q1. The NMOS transistor will charge the inductor L1 for 5µs, resulting in a peak current given by: (1) For reliable operation, L1 should be chosen so that IL(PEAK) does not exceed 1A. When the one-shot times out, the NMOS transistor releases the VL pin, allowing the inductor to fly-back and momentarily charge the output through the body diode of PMOS transistor Q2. But, as the voltage across the PMOS transistor changes polarity, its gate will be driven low by the current sense amplifier A2, causing Q2 to short out its body diode. The inductor then discharges into the load through Q2. The output of A2 also serves to reset the flip- flop and one-shot in preparation for the next charging cycle. A2 releases the gate of Q2 when its current falls to zero. If VOUT is still low, the flip-flop will immediately initiate another pulse. The output capacitor (C1) filters the inductor current, limiting output voltage ripple. Inductor current and one-shot waveforms are shown in Figure 3. RESET COMPARATOR An additional comparator is provided to detect low VIN, or any other error condition that is important to the user. The inverting input of the comparator is internally connected to VREF, while the non-inverting input is provided externally at the DETECT pin. The output of the comparator is the RESET pin, which swings from VOUT to GND when an error is detected. (Refer to Block Diagram) DESIGN CONSIDERATIONS INDUCTOR Selecting the proper inductor for a specific application usually involves a trade-off between efficiency and maximum output current. Choosing too high a value will keep the regulator from delivering the required output current under worst case conditions. Choosing too low a value causes efficiency to suffer. It is necessary to know the maximum required output current and the input voltage range to select the proper inductor value. The maximum inductor value can be estimated using the following formula: (2) where h is the efficiency, typically between 0.8 and 0.9. Note that this is the value of inductance that just barely delivers the required output current under worst case conditions. A lower value may be required to cover inductor tolerance, the effect of lower peak inductor currents caused by resistive losses, and minimum dead time between pulses. Another method of determining the appropriate inductor value is to make an estimate based on the typical performance curves given in Figures 4 and 5. Figure 4 shows maximum output current as a function of input voltage for several inductor values. These are typical performance curves and leave no margin for inductance and ON-time variations. To accommodate worst case conditions, it is necessary to derate these curves by at least 10% in addition to inductor tolerance. For example, a two cell to 5V application requires 60mA of output current while using an inductor with 15% tolerance. The output current should be derated by 25% to 80mA to cover the combined inductor and ON-time tolerances. Assuming that 2V is the end of life voltage of a two cell input, Figure 4 shows that with a 2V input, the ML4851-5 delivers 80mA with an 18µH inductor. Figure 5 shows efficiency under the conditions used to create Figure 4. It can be seen that efficiency is mostly independent of input voltage and is closely related to inductor value. This illustrates the need to keep the inductor value as high as possible to attain peak system efficiency. As the inductor value goes down to 10µH, the efficiency drops to around 75%. With 33µH, the efficiency exceeds 90% and there is little room for improvement. At values greater than 33µH, the operation of the synchronous rectifier becomes unreliable at low input voltages because the inductor current is so small that it is difficult for the control circuitry to detect. The data used to generate Figures 4 and 5 is provided in Table 1. I tV L sV L LPEAK ON IN IN () = × = × 1 5 1 µ L Vt VI MAX IN MIN ON MIN OUT OUT MAX = ×× ×× () () () 2 2 η |
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