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ML2721DH Datasheet(PDF) 6 Page - Micro Linear Corporation |
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ML2721DH Datasheet(HTML) 6 Page - Micro Linear Corporation |
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6 / 27 page  ML2721 6 January, 2000 PRELIMINARY DATASHEET PRELIMINARY PIN DESCRIPTIONS (continued) Power & Ground (Continued) 29 RVCC7 O (analog) DC power supply decoupling point for IF, Demodulator, and Data Slicer circuits. There must be a capacitor to ground from this pin to decouple (bypass) noise and to stabilize the regulator 25 GND I (analog) DC Ground to IF, Demodulator, and Data Slicer circuits 12 GND I (analog) Ground for the PLL dividers, phase detector, and charge pump 17 GND I (analog) Signal ground for RF small signal circuits. Pins 17, 18, and 19 should have short, direct connections to each other and additional connections to ground 18 GND I (analog) Ground return for the Receive RF input 19 GND I (analog) Signal ground for the Receive mixers 20 GND I (analog) DC and Signal ground for the Transmit RF Output buffer 31 VDD I (analog) DC power supply input to the interface logic and control registers. This supply is not internally connected to any other supply pin, but its voltage must be less than or equal to the VCC5 supply, and greater than 2.7V. There must be a capacitor to ground from this pin to decouple (bypass) noise and to stabilize the regulator 8 VSS I (digital) Ground for digital I/O circuits and control logic Transmit/Receive 21 RRFI I (analog) Receive RF Input. Nominal impedance at 902 to 928MHz is 50 W, with a simple matching network required for optimum noise figure. This input is to the base of an NPN transistor and should be AC coupled 23 TRFO O (analog) Transmit RF Output. A broadband 50 W output which sources 0dBm over the 902 to 928MHz range. This output is an emitter follower and should be AC coupled Data 30 DIN I (CMOS) Transmit Data input. Drives the transmit pulse shaping circuits. Serial digital data on this pin becomes FSK modulation on the Transmit RF output. Data timing is controlled by the logic timing on this pin. The modulation deviation is determined by internal circuits. This is a standard CMOS input referenced to VDD &VSS 32 DOUT O (CMOS) Serial digital output after demodulation, chip rate filtering and center data slicing. A CMOS level output (VSS to VDD) with controlled slew rates. A low drive output designed to drive a PCB trace and a CMOS logic input while generating minimal RFI. In digital test modes this pin becomes a test access port controlled by the serial control bus Mode Control and Interface Lines 1 XCEN I (CMOS) Enables the bandgap reference and voltage regulators when high. Consumes only leakage current in standby mode when low. This is a CMOS input, and the thresholds are referenced to VDD & VSS 2 RXON I (CMOS) Switches the transceiver between Transmit and Receive modes. Circuits are powered up and signal paths reconfigured according to the operating mode. This is a CMOS input, and the thresholds are referenced to VDD & VSS Pin # Signal Name I/O Description |
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