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TPS54620 Datasheet(PDF) 14 Page - Texas Instruments
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TPS54620 Datasheet(HTML) 14 Page - Texas Instruments
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SLVS949D – MAY 2009 – REVISED OCTOBER 2014
Feature Description (continued)
= 3.4 μA, I
= 1.15 μA, V
= 1.21 V, V
= 1.17 V
8.3.10 Adjustable Switching Frequency and Synchronization (RT/CLK)
The RT/CLK pin can be used to set the switching frequency of the device in two modes.
In RT mode, a resistor (RT resistor) is connected between the RT/CLK pin and GND. The switching frequency of
the device is adjustable from 200 kHz to 1600 kHz by placing a maximum of 240 k
Ω and minimum of 29 kΩ
respectively. In CLK mode, an external clock is connected directly to the RT/CLK pin. The device is synchronized
to the external clock frequency with PLL.
The CLK mode overrides the RT mode. The device is able to detect the proper mode automatically and switch
from the RT mode to CLK mode.
8.3.11 Slow Start (SS/TR)
The device uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the reference
voltage and regulates the output accordingly. A capacitor on the SS/TR pin to ground implements a slow start
time. The device has an internal pull-up current source of 2.3
μA that charges the external slow start capacitor.
The calculations for the slow start time (Tss, 10% to 90%) and slow start capacitor (Css) are shown in
Equation 4. The voltage reference (Vref) is 0.8 V and the slow start charge current (Iss) is 2.3
When the input UVLO is triggered, the EN pin is pulled below 1.21V, or a thermal shutdown event occurs the
device stops switching and enters low current operation. At the subsequent power up, when the shutdown
condition is removed, the device does not start switching until it has discharged its SS/TR pin to ground ensuring
proper soft start behavior.
8.3.12 Power Good (PWRGD)
The PWRGD pin is an open drain output. Once the VSENSE pin is between 94% and 106% of the internal
voltage reference the PWRGD pin pull-down is de-asserted and the pin floats. It is recommended to use a pull-
up resistor between the values of 10k
Ω and 100kΩ to a voltage source that is 5.5V or less. The PWRGD is in a
defined state once the VIN input voltage is greater than 1V but with reduced current sinking capability. The
PWRGD achieves full current sinking capability once the VIN input voltage is above 4.5V.
The PWRGD pin is pulled low when VSENSE is lower than 91% or greater than 109% of the nominal internal
reference voltage. Also, the PWRGD is pulled low, if the input UVLO or thermal shutdown are asserted, the EN
pin is pulled low or the SS/TR pin is below 1.4V.
8.3.13 Output Overvoltage Protection (OVP)
The device incorporates an output overvoltage protection (OVP) circuit to minimize output voltage overshoot. For
example, when the power supply output is overloaded the error amplifier compares the actual output voltage to
the internal reference voltage. If the VSENSE pin voltage is lower than the internal reference voltage for a
considerable time, the output of the error amplifier demands maximum output current. Once the condition is
removed, the regulator output rises and the error amplifier output transitions to the steady state voltage. In some
applications with small output capacitance, the power supply output voltage can respond faster than the error
amplifier. This leads to the possibility of an output overshoot. The OVP feature minimizes the overshoot by
comparing the VSENSE pin voltage to the OVP threshold. If the VSENSE pin voltage is greater than the OVP
threshold the high-side MOSFET is turned off preventing current from flowing to the output and minimizing output
overshoot. When the VSENSE voltage drops lower than the OVP threshold, the high-side MOSFET is allowed to
turn on at the next clock cycle.
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