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TPS54331 Datasheet(PDF) 4 Page - Texas Instruments |
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TPS54331 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 36 page 1 2 3 4 5 6 7 8 BOOT VIN EN SS PH GND COMP VSENSE PowerPAD (Pin 9) TM 1 2 3 4 5 6 7 8 BOOT VIN EN SS PH GND COMP VSENSE TPS54331 SLVS839F – JULY 2008 – REVISED OCTOBER 2014 www.ti.com 6 Pin Configuration and Functions D Package DDA Package 8-Pin SOIC 8-Pin SO With PowerPAD™ Top View Top View Pin Functions PIN I/O DESCRIPTION NO. NAME A 0.1- μF bootstrap capacitor is required between the BOOT and PH pins. If the voltage on this 1 BOOT O capacitor falls below the minimum requirement, the high-side MOSFET is forced to switch off until the capacitor is refreshed. 2 VIN I This pin is the 3.5- to 28-V input supply voltage. This pin is the enable pin. To disable, pull below 1.25 V. Float this pin to enable. Programming 3 EN I the input undervoltage lockout with two resistors is recommended. 4 SS I This pin is slow-start pin. An external capacitor connected to this pin sets the output rise time. 5 VSENSE I This pin is the inverting node of the transconductance (gm) error amplifier. This pin is the error-amplifier output and the input to the PWM comparator. Connect frequency 6 COMP O compensation components to this pin. 7 GND — Ground pin 8 PH O The PH pin is the source of the internal high-side power MOSFET. The PowerPAD is only available on the DDA package. For proper operation, the GND pin 9 PowerPAD™ — must be connected to the exposed pad 4 Submit Documentation Feedback Copyright © 2008–2014, Texas Instruments Incorporated Product Folder Links: TPS54331 |
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