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F20 Datasheet(PDF) 69 Page - List of Unclassifed Manufacturers |
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F20 Datasheet(HTML) 69 Page - List of Unclassifed Manufacturers |
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69 / 111 page  Boxchip F20 Datasheet Boxchip. All rights reserved. Ver 1.01 Page 69 14. SD3.0 Controller 14.1. SD3.0 Controller Overview The SD3.0 controller can be configured either as a Secure Digital Multimedia Card controller, which simultaneously supports Secure Digital memory (SD Memo), UHS-1 Card, Secure Digital I/O (SDIO), Multimedia Cards (MMC), eMMC Card and Consumer Electronics Advanced Transport Architecture (CE-ATA). The SD3.0 controller includes the following features: Supports Secure Digital memory protocol commands (up to SD3.0) Supports Secure Digital I/O protocol commands Supports Multimedia Card protocol commands (up to MMC4.3) Supports CE-ATA digital protocol commands Supports eMMC boot operation and alternative boot operation Supports UHS-1card voltage switching and DDR R/W operation Supports Command Completion signal and interrupt to host processor and Command Completion Signal disable feature Supports one SD (Verson1.0 to 3.0) or MMC (Verson3.3 to 4.3) or CE-ATA device Supports hardware CRC generation and error detection Supports programmable baud rate Supports host pull-up control Supports SDIO interrupts in 1-bit and 4-bit modes Supports SDIO suspend and resume operation Supports SDIO read wait Supports block size of 1 to 65535 bytes Supports descriptor-based internal DMA controller Internal 16x32-bit (64 bytes total) FIFO for data transfer Support 3.3 V and 1.8V IO pad 14.2. SD3.0 Controller Signal Description Table 14-1. NAND Flash Controller Signal Description Signal Name Description Type Pin Name Ball# SD0/SDIO0/MMC0(3.0) SDC0_CLK SD0/SDIO0/MMC0 Output Clock O PF2 Y11 SDC0_CMD SD0/SDIO0/MMC0 Cmmand Line I/O PF3 Y12 SDC0_D0 SD0/SDIO0/MMC0 Data bit0 I/O PF1 W11 SDC0_D1 SD0/SDIO0/MMC0 Data bit1 I/O PF0 V11 SDC0_D2 SD0/SDIO0/MMC0 Data bit2 I/O PF5 V12 SDC0_D3 SD0/SDIO0/MMC0 Data bit3 I/O PF4 W12 |
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