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TPS54010-EP Datasheet(PDF) 6 Page - Texas Instruments |
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TPS54010-EP Datasheet(HTML) 6 Page - Texas Instruments |
6 / 31 page 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AGND VSENSE COMP PWRGD BOOT PH PH PH PH PH PH PH PH PH RT SYNC SS/ENA VBIAS VIN PVIN PVIN PVIN PVIN PGND PGND PGND PGND PGND THERMAL PAD TPS54010-EP SLVSBN3 – JANUARY 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TJ = -55°C to 125°C, VIN = 3 V to 4 V, PVIN = 2.2 V to 4 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT POWER MOSFETS VIN = 3 V, PVIN = 2.5 V 8 21 rDS(on) Power MOSFET switches m Ω VIN = 3.6 V, PVIN = 2.5 V 8 18 DEVICE INFORMATION PWP PACKAGE (TOP VIEW) TERMINAL FUNCTIONS PIN NAME PIN NUMBER DESCRIPTION Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, and AGND 1 RT resistor. If using the PowerPAD, connect it to AGND. See the Application Information section for details. Bootstrap output. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating BOOT 5 drive for the high-side FET driver. COMP 3 Error amplifier output. Connect frequency compensation network from COMP to VSENSE Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large 15, 16, 17, 18, PGND copper areas to the input and output supply returns, and negative terminals of the input and output 19 capacitors. A single point connection to AGND is recommended. PH 6-14 Phase output. Junction of the internal high-side and low-side power MOSFETs, and output inductor. Input supply for the power MOSFET switches and internal bias regulator. Bypass the PVIN pins to the PVIN 20, 21, 22, 23 PGND pins close to device package with a high-quality, low-ESR 10-µF ceramic capacitor. Power-good open-drain output. High when VSENSE > 90% Vref, otherwise PWRGD is low. Note that PWRGD 4 output is low when SS/ENA is low or the internal shutdown signal is active. RT 28 Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, fs. Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device SS/ENA 26 operation and capacitor input to externally set the start-up time. Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator SYNC 27 or pin select between two internally set switching frequencies. When used to synchronize to an external signal, a resistor must be connected to the RT pin. Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND VBIAS 25 pin with a high-quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor. Input supply for the internal control circuits. Bypass the VIN pin to the PGND pins close to device package VIN 24 with a high-quality, low-ESR 1-µF ceramic capacitor. VSENSE 2 Error amplifier inverting input. Connect to output voltage compensation network/output divider. 6 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS54010-EP |
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