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TPS51650 Datasheet(PDF) 10 Page - Texas Instruments

Part # TPS51650
Description  Dual-Channel (3-Phase CPU/2-Phase GPU) SVID, D-CAP??Step-Down Controller for IMVP-7 VCORE with Two Integrated Drivers
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TPS51650 Datasheet(HTML) 10 Page - Texas Instruments

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CTHERM
COCP-R
CF-IMAX
CCSP1
CCSN1
CCSN2
CCSP2
CCSP3
CCSN3
CVFB
CCOMP
CGFB
CPWM3
GPWM2
GPWM1
GSKIP
GTHERM
GCSN2
GCSP2
GCSP1
GCSN1
GCOMP
GVFB
GGFB
TPS51650
TPS51650, TPS59650
SLUSAV7
– JANUARY 2012
www.ti.com
DEVICE INFORMATION
RSL PACKAGE
48 PINS
(TOP VIEW)
PIN FUNCTIONS
PIN
I/O
DESCRIPTION
NAME
NO.
ALERT
19
O
SVID interrupt line, open drain. Route between VCLK and VDIO to prevent cross-talk.
CBST1
46
I
Top N-channel FET bootstrap voltage input for CPU phase 1.
CBST2
39
I
Top N-channel bootstrap voltage input for CPU phase 2.
CCSN1
5
Negative current sense inputs for the CPU converter. Connect to the most negative node of current sense
CCSN2
6
I
resistor or inductor DCR sense network. CCSN1 has a secondary OVP comparator.
CCSN3
9
CCOMP
10
O
Output of GM error amplifier for the CPU converter. A resistor to VREF sets the droop gain.
CCSP1
4
Positive current sense inputs for the CPU converter. Connect to the most positive node of current sense resistor
CCSP2
7
I
or inductor DCR sense network. Tie CCSP3, 2 or 1 (in that order) to V3R3 to disable the phase. Tie CCSP1 to
V3R3 to run the GPU converter only.
CCSP3
8
CDH1
47
O
Top N-channel FET gate drive output for CPU phase 1.
CDH2
38
O
Top N-channel FET gate drive output for CPU phase 2.
CDL1
44
O
Synchronous N-channel FET gate drive output for CPU phase 1.
CDL2
41
O
Synchronous N-channel FET gate drive output for CPU phase 2.
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Copyright
© 2012, Texas Instruments Incorporated


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