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TC1791 Datasheet(PDF) 10 Page - Infineon Technologies AG |
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TC1791 Datasheet(HTML) 10 Page - Infineon Technologies AG |
10 / 153 page TC1791 Summary of Features Data Sheet 3 V 1.1, 2014-05 – 200 MHz operation at full temperature range • Multiple on-chip memories – 4 Mbyte Program Flash Memory (PFLASH) with ECC – 192 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation – 2 x 8 Kbyte Key Flash – 128 Kbyte Data Scratch-Pad RAM (DSPR) – 16 Kbyte Instruction Cache (ICACHE) – 32 Kbyte Instruction Scratch-Pad RAM (PSPR) – 16 Kbyte Data Cache (DACHE) – 128 Kbyte Memory (SRAM) – 16 Kbyte BootROM (BROM) • 16-Channel DMA Controller • 8-Channel Safe DMA (SDMA) Controller • Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels serviced by CPU or PCP2 • High performing on-chip bus structure – 64-bit Cross Bar Interconnect between CPU, Flash and Data Memory – 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units – One bus bridge (SFI Bridge) • Versatile On-chip Peripheral Units – Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator, parity, framing and overrun error detection – Four High-Speed Synchronous Serial Channels (SSC) with programmable data length and shift direction – Four SSC Guardian (SSCG) modules, one for each SSC – Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external power devices – Two High-Speed Micro Link interfaces (MLI) for serial inter-processor communication – One MultiCAN Module with 4 CAN nodes and 128 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer (one CAN node supports TTCAN functionality) – One FlexRayTM module with 2 channels (E-Ray). – Two General Purpose Timer Array Modules (GPTA) with additional Local Timer Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input/Output management – Two Capture / Compare 6 modules – Two General Purpose 12 Timer Units (GPT120 and GPT121) • 44 analog input lines for ADC – 4 independent kernels (ADC0, ADC1, and ADC2) – Analog supply voltage range from 3.3 V to 5 V (single supply) • 4 different FADC input channels – channels with impedance control and overlaid with ADC1 inputs |
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