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TC1724 Datasheet(PDF) 11 Page - Infineon Technologies AG |
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TC1724 Datasheet(HTML) 11 Page - Infineon Technologies AG |
11 / 134 page TC1724 Summary of Features Data Sheet 1-6 V1.2, 2014-06 – Two General Purpose Timer (GPT12) modules • 28 analog input lines for ADC – 2 independent kernels (ADC0 and ADC1) – Analog supply voltage range from 3.3 V to 5 V (single supply) • 2 different FADC input channels – channels with impedance control and overlaid with ADC1 inputs – Extreme fast conversion, 21 cycles of fFADC clock – 10-bit A/D conversion (higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter) • 95 digital general purpose I/O lines (GPIO) • Digital I/O ports with 3.3 V capability • On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Bus) • Dedicated Emulation Device chip available (TC1724ED) – multi-core debugging, real time tracing, and calibration – four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface • Power Management System • Clock Generation Unit with PLL |
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