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TPS40322 Datasheet(PDF) 3 Page - Texas Instruments

Part No. TPS40322
Description  Dual Output or Two-Phase Synchronous Buck Controller
Download  42 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TPS40322 Datasheet(HTML) 3 Page - Texas Instruments

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TPS40322
www.ti.com
SLUSAF8D – JUNE 2011 – REVISED JANUARY 2014
THERMAL INFORMATION
TPS40322
THERMAL METRIC(1)
QFN
UNITS
32 PINS
θJA
Junction-to-ambient thermal resistance(2)
37.3
θJCtop
Junction-to-case (top) thermal resistance(3)
28.6
θJB
Junction-to-board thermal resistance(4)
10.0
°C/W
ψJT
Junction-to-top characterization parameter(5)
0.4
ψJB
Junction-to-board characterization parameter(6)
9.9
θJCbot
Junction-to-case (bottom) thermal resistance(7)
2.7
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2)
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3)
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4)
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5)
The junction-to-top characterization parameter,
ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6)
The junction-to-board characterization parameter,
ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7)
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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Copyright © 2011–2014, Texas Instruments Incorporated
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