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TPS40322 Datasheet(PDF) 24 Page - Texas Instruments

Part No. TPS40322
Description  Dual Output or Two-Phase Synchronous Buck Controller
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TPS40322 Datasheet(HTML) 24 Page - Texas Instruments

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SS
SS
SS
FB
t
I
2ms
10 A
C
33 nF
V
0.6 V
´
´
m
=
=
»
9
9
RT
SW
20
20
R
40 k
40.2k
f
500 kHz
=
=
=
W »
W
(
)
G1
BOOST
BOOT ripple
Q
7nC
C
70nF
100nF
V
100mV
=
=
=
»
FB
OUT1
FB
V
R10
0.600 V
20.0 k
R14
20 k
V
V
1.2 V
0.600 V
´
´
W
=
=
=
W
-
-
(
)
(
)
(
)
(
)
(
)
OC
CS
OS min
LIM
ILIM min
V
V
A
51.05 mV
3 mV
15 V V
R
85.3 k
86.6 k
I
9.5 A
-
´
- -
´
=
=
=
W @
W
m
TPS40322
SLUSAF8D – JUNE 2011 – REVISED JANUARY 2014
www.ti.com
The current limit resistor is calculated using the minimum ILIM programming current, IILIM(min), the maximum
current sense amplifier gain, ACS, and assuming a current sense amplifier minimum input offset voltage, VOS(min)
equal to –3 mV.
(24)
Feedback Divider (R10, R14)
The TPS40322 controller uses a full operational amplifier with an internally fixed 0.600-V reference. Tha value for
R10 is selected between 10-k
Ω and 50-kΩ for a balance of feedback current and noise immunity. With the R10
resistor set to 20-k
Ω, the output voltage is programmed with a resistor divider given by Equation 25.
(25)
Compensation: (R11, R12, C17, C19, C21)
Using the TPS40k Loop Stability Tool for an 85-kHz bandwidth and 50° of phase margin with an R10 value of
20.0 k
Ω, and measuring the theoretical results in the laboratory and modifying accordingly for system
optimization yields the following values.
C21 = 10 pF
C17 = 220 pF
C19 = 470 pF
R12 = 4.42 k
Ω
R11 = 82.5 k
Ω
Boot-Strap Capacitor (C7)
To ensure proper charging of the high-side FET gate, limit the ripple voltage on the boost capacitor to < 100 mV.
(26)
General Device Components
Synchronization (SYNC Pin)
The SYNC pin should be left open for independent dual outputs.
RT Resistor (R6)
The desired switching frequency is programmed by the current through RRT to GND. the value of RRT is
calculated using Equation 27.
(27)
Differential Amplifier Out (DIFFO Pin)
In dual output configuration the DIFFO pin is not used and must remain open (unconnected).
EN/SS Timing Capacitors (C8)
The soft-start capacitor provides smooth ramp of the error amplifier reference voltage for controlled start-up. The
soft-start capacitor is selected using Equation 28.
(28)
24
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Copyright © 2011–2014, Texas Instruments Incorporated


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