TPS40140_15 datasheet(44/71 Pages) TI | TPS40140 Dual or 2-Phase, Stackable Controller

Part #	TPS40140

Description	TPS40140 Dual or 2-Phase, Stackable Controller

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Manufacturer	TI [Texas Instruments]

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OUT

s

OUT

(s × C

× ESR + 1) × R

1

Gvc(s) =

×

DCR × Ac

s × τ + 1

s × C

× (ESR +R

) + 1

(

)

3

9

3

SS

t

C

58

10

22

10

58

10

1.28 ms

-

=

´

=

´

=

boot

Qg

8nc

C

=

= 16 nF

V

0.5V

TPS40140

SLUS660I – SEPTEMBER 2005 – REVISED JANUARY 2015

www.ti.com

9.2.1.2.5.5

VREG (Pin 21)

A 4.7-

μF capacitor is connected to VREG pin to filter noise.

9.2.1.2.5.6

BP5 (Pin 8)

A 4.7-

Ω and 1-μF capacitor is placed between VREG and BP5.

9.2.1.2.5.7

PHSEL (Pin 4)

For this dual output configuration, the PHSEL pin is directly tied to GND. The channel 1 and channel 2 has a

180° phase shift.

9.2.1.2.5.8

VSHARE (Pin 6)

A 1-

μF capacitor is tied from VSHARE pin to GND.

9.2.1.2.5.9

PGOOD1 (Pin 30)

The PGOOD1 pin is tied to BP5 with a 10-k

Ω resistor.

9.2.1.2.5.10

UVLO_CE1 (Pin 29)

It is connected to the input voltage with a resistor divider. The two resistors have the same value of 10-k

Ω. When

the input voltage is higher than 2 V, the chip is enabled.

9.2.1.2.5.11

Clkio (Pin 28)

CLKIO is floating as no clock synchronization required for dual output configuration.

9.2.1.2.5.12

BOOT1 and SW1 (Pin 27 and 25)

A bootstrap capacitor is connected between the BOOT1 and SW1 pin. The bootstrap capacitor depends on the

total gate charge of the high side MOSFET and the amount of droop allowed on the bootstrap capacitor.

(44)

For this application, a 0.1-

μF capacitor is selected.

9.2.1.2.5.13

TRK1 (Pin 33)

A 22-nF capacitor is tied to TRK1 pin to provide 1.28-ms of soft-start time.

(45)

9.2.1.2.5.14

DIFFO, VOUT, and GSNS (Pin 1, Pin 2, and Pin 3)

VOUT and GSNS are connected to the remote sensing output connector. DIFFO is connected to the feedback

resistor divider. If the differential amplifier is not used, VOUT and GSNS are suggested to be grounded, and

DIFFO is left open.

9.2.1.2.6

Feedback Compensator Design (COMP1 Pin 35)

Peak current mode control method is employed in the controller. A small signal model is developed from the

COMP signal to the output.

(46)

The time constant is defined by:

44

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