TPS5410

SLVS675D – AUGUST 2006 – REVISED DECEMBER 2014

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Feature Description (continued)

7.3.9 Pulse-Width-Modulation (PWM) Control

The regulator employs a fixed frequency pulse-width-modulator (PWM) control method. First, the feedback

voltage (VSENSE pin voltage) is compared to the constant voltage reference by the high gain error amplifier and

compensation network to produce a error voltage. Then, the error voltage is compared to the ramp voltage by the

PWM comparator. In this way, the error voltage magnitude is converted to a pulse width which is the duty cycle.

Finally, the PWM output is fed into the gate drive circuit to control the on-time of the high-side MOSFET.

7.3.10 Overcurrent Liming

Overcurrent limiting is implemented by sensing the drain-to-source voltage across the high-side MOSFET. The

drain to source voltage is then compared to a voltage level representing the overcurrent threshold limit. If the

drain-to-source voltage exceeds the overcurrent threshold limit, the overcurrent indicator is set true. The system

will ignore the overcurrent indicator for the leading edge blanking time at the beginning of each cycle to avoid any

turn-on noise glitches.

Once overcurrent indicator is set true, overcurrent limiting is triggered. The high-side MOSFET is turned off for

the rest of the cycle after a propagation delay. The overcurrent limiting scheme is called cycle-by-cycle current

limiting.

Sometimes under serious overload conditions such as short-circuit, the overcurrent runaway may still happen

when using cycle-by-cycle current limiting. A second mode of current limiting is used, for example hiccup mode

overcurrent limiting. During hiccup mode overcurrent limiting, the voltage reference is grounded and the high-side

MOSFET is turned off for the hiccup time. Once the hiccup time duration is complete, the regulator restarts under

control of the slow-start circuit.

7.3.11 Overvoltage Protection

The TPS5410 has an overvoltage protection (OVP) circuit to minimize voltage overshoot when recovering from

output fault conditions. The OVP circuit includes an overvoltage comparator to compare the VSENSE pin voltage

and a threshold of 112.5% x VREF. Once the VSENSE pin voltage is higher than the threshold, the high-side

MOSFET will be forced off. When the VSENSE pin voltage drops lower than the threshold, the high-side

MOSFET will be enabled again.

7.3.12 Thermal Shutdown

The TPS5410 protects itself from overheating with an internal thermal shutdown circuit. If the junction

temperature exceeds the thermal shutdown trip point, the voltage reference is grounded and the high-side

MOSFET is turned off. The part is restarted under control of the slow-start circuit automatically when the junction

temperature drops 14°C below the thermal shutdown trip point.

7.4 Device Functional Modes

7.4.1 Minimum Input Voltage

Confid The TPS5410 is recommended to operate with input voltages above 5.5 V. The typical VIN UVLO

threshold is 5.3 V and the device may operate at input voltages down to the UVLO voltage. At input voltages

below the actual UVLO voltage the device will not switch. If ENA is floating or externally pulled up to greater up

the slow-start sequence is initiated. The TPS5410 starts linearly ramping up the internal reference voltage from 0

V to its final value over the internal slow-start time period.

7.4.2 ENA Control

T The enable start threshold voltage is 1.3 V max. With ENA held below the 0.5 V minimum stop threshold

voltage the TPS5410 is disabled and switching is inhibited even if VIN is above its UVLO threshold. The

quiescent current is reduced in this state. If the ENA voltage is increased above the max start threshold while

sequence is initiated. The TPS5410 starts linearly ramping up the internal reference voltage from 0 V to its final

value over the internal slow-start time period.

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