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LMR14203 Datasheet(PDF) 8 Page - Texas Instruments |
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LMR14203 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 17 page LMR14203 SNVS732C – OCTOBER 2011 – REVISED APRIL 2013 www.ti.com available with a bigger winding area. A good tradeoff between the efficiency and the core size is letting the inductor copper loss equal 2% of the output power. See AN-1197 SNVA038 for more information on selecting inductors. A good starting point for most applications is a 10 µH to 22 µH with a 0.7A or greater current rating for the LMR14203. Using such a rating will enable the LMR14203 to current limit without saturating the inductor. This is preferable to the device going into thermal shutdown mode and the possibility of damaging the inductor if the output is shorted to ground or other longterm overload. Output Capacitor The selection of COUT is driven by the maximum allowable output voltage ripple. The output ripple in the constant frequency, PWM mode is approximated by: VRIPPLE = IRIPPLE(ESR+(1/(8fSWCOUT))) (4) The ESR term usually plays the dominant role in determining the voltage ripple. Low ESR ceramic capacitors are recommended. Capacitors in the range of 22 µF-100 µF are a good starting point with an ESR of 0.1 Ω or less. Bootstrap Capacitor A 0.15 µF ceramic capacitor or larger is recommended for the bootstrap capacitor (CBOOT). For applications where the input voltage is less than twice the output voltage a larger capacitor is recommended, generally 0.15 µF to 1 µF to ensure plenty of gate drive for the internal switches and a consistently low RDSON. Soft-Start Components The LMR14203 has circuitry that is used in conjunction with the SHDN pin to limit the inrush current on start-up of the DC/DC switching regulator. The SHDN pin in conjunction with a RC filter is used to tailor the soft-start for a specific application. When a voltage applied to the SHDN pin is between 0V and up to 2.3V it will cause the cycle by cycle current limit in the power stage to be modulated for minimum current limit at 0V up to the rated current limit at 2.3V. Thus controlling the output rise time and inrush current at startup. The resistor value should be selected so the current sourced into the SHDN pin will be greater then the leakage current of the SHDN pin (1.5 µA ) when the voltage at SHDN is equal or greater then 2.3V. Shutdown Operation The SHDN pin of the LMR14203 is designed so that it may be controlled using 2.3V or higher logic signals. If the shutdown function is not to be used the SHDN pin may be tied to VIN. The maximum voltage to the SHDN pin should not exceed 42V. If the use of a higher voltage is desired due to system or other constraints it may be used, however a 100 k Ω or larger resistor is recommended between the applied voltage and the SHDN pin to protect the device. SCHOTTKY Diode The breakdown voltage rating of the diode (D1) is preferred to be 25% higher than the maximum input voltage. The current rating for the diode should be equal to the maximum output current for best reliability in most applications. In cases where the duty cycle is greater than 50%, the average diode current is lower. In this case it is possible to use a diode with a lower average current rating, approximately (1-D)IOUT, however the peak current rating should be higher than the maximum load current. A 0.5A to 1A rated diode is a good starting point. Layout Considerations To reduce problems with conducted noise pick up, the ground side of the feedback network should be connected directly to the GND pin with its own connection. The feedback network, resistors R1 and R2, should be kept close to the FB pin, and away from the inductor to minimize coupling noise into the feedback pin. The input bypass capacitor CIN must be placed close to the VIN pin. This will reduce copper trace resistance which effects input voltage ripple of the IC. The inductor L1 should be placed close to the SW pin to reduce EMI and capacitive coupling. The output capacitor, COUT should be placed close to the junction of L1 and the diode D1. The L1, D1, and COUT trace should be as short as possible to reduce conducted and radiated noise and increase overall efficiency. The ground connection for the diode, CIN, and COUT should be as small as possible and tied to the system ground plane in only one spot (preferably at the COUT ground point) to minimize conducted noise in the system ground plane. For more detail on switching power supply layout considerations see Application Note AN- 1149: Layout Guidelines for Switching Power Supplies SNVA021. 8 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMR14203 |
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