D3

D2

A3

A2

D1

C1

A1

B1

C2

B2

C3

B3

A3

A2

D3

D2

A1

B1

C1

D1

C2

B2

C3

B3

LM3686

www.ti.com

SNVS520E – AUGUST 2008 – REVISED MAY 2013

Connection Diagram

Figure 3. 12-pin DSBGA Package

See Package Number YZR0012

ORDERING INFORMATION

PART NUMBER

VOLTAGE OPTIONS

1.8V_Bk

LM3686TL/TLX-AADW

1.2V_LILO

2.8V_LDO

1.2V_Bk

LM3686TLE/TLX-AAED

1.8V_LILO

2.8V_LDO

1.8V_Bk

LM3686TLE/TLXX-AAEF

1.2V_LILO

3.0V_LDO

PIN DESCRIPTIONS

Pin Number

Symbol

Name and Function

A1

PGND

Power Ground pin

A2

SW

Switching node connection to the internal PFET switch and NFET synchronous rectifier.

A3

FB_DCDC

Feedback analog input for the DC-DC converter. Connect to the output filter capacitor.

B1

Power supply input for switcher. Connect to the input filter capacitor.

B2

EN_LILO

Enable input for the linear regulator. The linear regulator is in shutdown mode if voltage at this pin is

< 0.4V and enabled if > 1.1V. Do not leave this pin floating.

B3

EN_DCDC

Enable input for the DC-DC converter. The DC-DC converter is in shutdown mode if voltage at this pin is <

0.4V and enabled if > 1.1V. Do not leave this pin floating.

C1

C2

EN_LDO

Enable input for the linear regulator. The linear regulator is in shutdown mode if voltage at this pin is

< 0.4V and enabled if > 1.1V. Do not leave this pin floating.

C3

QGND

Quiet GND pin for LDO and reference circuit.

D1

Voltage output of the linear regulator.

D2

Voltage output of the low input linear regulator

D3

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