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LM3253 Datasheet(PDF) 6 Page - Texas Instruments

Part # LM3253
Description  LM3253 High-Current Step-Down Converter for 2G/3G/4G RF Power Amplifiers
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

LM3253 Datasheet(HTML) 6 Page - Texas Instruments

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LM3253
SNVS791Q – FEBRUARY 2012 – REVISED MAY 2013
www.ti.com
ELECTRICAL CHARACTERISTICS
(1) (2) (3)
Limits in standard typeface are for TA = TJ = 25°C. Limits in boldface type apply over the full operating ambient temperature
range (
−30°C ≤ TA = TJ ≤ +90°C). Unless otherwise noted, all specifications apply to the Typical System Application Diagram
with: PVIN = VDD = EN = 3.8V, BP = 0V.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Feedback voltage at low
VFB, LOW
VCON = 0.16V, MODE = LOW(3)
0.3500
0.400
0.450
V
setting
Feedback voltage at high
VCON = 1.4V, VIN = 3.9V,
VFB, HIGH
3.492
3.6
3.708
V
setting
MODE = LOW(3)
ISHDN
Shutdown supply current
EN = SW = VCON = 0V(4)
0.02
4
µA
No switching(5)
Iq_PFM
DC bias current into VDD
260
310
MODE = HIGH
µA
No Switching (5)
Iq_PWM
DC bias current into VDD
975
1100
MODE = LOW
Positive transient peak current
ILIM,PFET, Transient
VCON = 0.6V(6)
2.3
2.5
A
limit
ILIM,PFET,Steady
Positive steady state peak
VCON = 0.6V(6)
1.78
1.9
2.09
A
State
current limit
Positive active current assist
VCON = 0.6V,
ILIM, P_ACB
1.40
1.70
2.00
A
peak current limit
VACB = 2.8V(6)
NFET Switch negative peak
ILIM, NFET
VCON = 1.0V(6)
−1.69
−1.50
−1.31
A
current limit
Average internal oscillator
FOSC
VCON = 1.0V
2.43
2.70
2.97
MHz
frequency
VIH
Logic HIGH input threshold
BP, EN, MODE
1.2
V
VIL
Logic LOW input threshold
BP, EN, MODE
0.5
IEN
EN pin pulldown current
EN = 3.6V
0
5
10
IIN
Pin input current
BP, MODE
−1
1
µA
IVCON
VCON pin leakage current
VCON = 1.0V
−1
1
Gain
VCON to VOUT Gain
0.16V
≤ VCON ≤ 1.44V(6)
2.5
V/V
(1)
All voltages are with respect to the potential at the GND pins. The LM3253 is designed for mobile phone applications where turn-on after
power-up is controlled by the system controller and where requirements for a small package size overrule increased die size for internal
Under Voltage Lock-Out (UVLO) circuitry. Thus, it should be kept in shutdown by holding the EN pin LOW until the input voltage
exceeds 2.7V.
(2)
Min and Max limits are specified by design, test, or statistical analysis.
(3)
The parameters in the electrical characteristics table are tested under open loop conditions at PVIN = VIN = 3.8V. For performance over
the input voltage range and closed-loop results, refer to the datasheet curves.
(4)
Shutdown current includes leakage current of PFET.
(5)
Iq specified here is when the part is not switching. For operating input current at no load, refer to datasheet curves.
(6)
Current limit is built-in, fixed, and not adjustable.
6
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