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TPS3700-Q1 Datasheet(PDF) 3 Page - Texas Instruments |
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TPS3700-Q1 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 28 page 1 2 3 6 5 4 OUTA GND INA+ OUTB VDD INB - 1 2 3 6 5 4 OUTB VDD INB - OUTA GND INA+ TPS3700 www.ti.com SBVS187D – FEBRUARY 2012 – REVISED JANUARY 2015 6 Pin Configuration and Functions DDC Package DSE Package SOT-6 WSON-6 (Top View) (Top View) Pin Functions PIN I/O DESCRIPTION NAME DDC DSE GND 2 5 — Ground This pin is connected to the voltage to be monitored with the use of an external resistor INA+ 3 4 I divider. When the voltage at this terminal drops below the threshold voltage (VITP – VHYS), OUTA is driven low. This pin is connected to the voltage to be monitored with the use of an external resistor INB– 4 3 I divider. When the voltage at this terminal exceeds the threshold voltage (VITP), OUTB is driven low. INA+ comparator open-drain output. OUTA is driven low when the voltage at this OUTA 1 6 O comparator is below (VITP – VHYS). The output goes high when the sense voltage returns above the respective threshold (VITP). INB– comparator open-drain output. OUTB is driven low when the voltage at this OUTB 6 1 O comparator exceeds VITP. The output goes high when the sense voltage returns below the respective threshold (VITP – VHYS). Supply voltage input. Connect a 1.8-V to 18-V supply to VDD to power the device. Good VDD 5 2 I analog design practice is to place a 0.1-µF ceramic capacitor close to this pin. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPS3700 |
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