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FEDL22340-02 Datasheet(PDF) 5 Page - List of Unclassifed Manufacturers |
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FEDL22340-02 Datasheet(HTML) 5 Page - List of Unclassifed Manufacturers |
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5 / 37 page  FEDL22340-02 ML22Q340/340/Q341/341 5/37 PIN DESCRIPTIONS Pin No. symbol I/O Description 11 RESET_N I Place this pin at a “L” level when powered on. After the supply voltage is settled, place this pin at a “H” level. 17 16 15 14 13 EVIN0 EVIN1 EVIN2 EVIN3 EVIN4 I Event specifying input pins. Event execution or stop can be performed by changes in the input signals to the activation pins set by the EVIN0 pin or Mask option Set the unused pins to be pulled up or pulled down. And the SEQ0 pin can specify only the SEQ pattern 6. 12 TEST I Input pin for testing. Fix this pin at a “L” level (GND level). 2 OSC0 I Pin for connecting a crystal or a ceramic vibrator. A feed back resistor (about 1 M Ω) is included between OSC0 and OSC1 pins. When a vibrator is used, place it as close to the LSI as possible. 3 OSC1 O Pin for connecting a crystal or a ceramic vibrator. When a vibrator is used, place it as close to the LSI as possible. 6 ERR O Error output pin for thermal detection and disconnection detection. If disconnection detection or a higher temperature than the judgment temperature is detected, this pin output “H”. Setting event 1 , operate the disconnection detection. And the 100ms “H” pulse is output right after the event start. 7 8 9 SEQ0 SEQ1 SEQ2 O Sequencer output pins. This pin is output SEQ pattern 01h~10h based on ROM data. The SEQ patterns (01h to 10h) set by Mask option are output. And the SEQ0 pin can specify only the SEQ pattern 6. 18 19 20 21 SEQ3/LED0 SEQ4/LED1 SEQ5/LED2 SEQ6/LED3 O Sequencer output pins. These pins can drive LED. The patterns set by Mask option are output. 24 AOUT O Playback signal output pin. When you use built-in speaker amplifier, connect with the SPIN pin. 5 VPP *Note 1 — Power supply pin for rewriting Flash memory. Fix this pin to GND except when rewriting Flash memory. 1 VDD — Digital power supply pin. Connect a capacitor of 0.1 µF or more between this pin and GND. 4 VDDL — Output pin of the regulator for the internal logic power supply. Connect a electrolytic capacitor of 10 uF or more and a ceramic capacitor of 0.1 µF or more between the VDDL and GND pins. 10,22 GND — Digital ground pin. 27 SPGND — Speaker amplifier ground pin. 26 SPVDD — Speaker amplifier power supply pin. 25 SPIN I Analog input pin of internal speaker amplifier. 23 SG O Built-in speaker amplifier’s reference voltage output pin. Connect a capacitor of 0.1 µF or more between this pin and GND. 30 SPP O Positive output pin of the built-in speaker amplifier. 29 SPM O Negative output pin of the built-in speaker amplifier. Notes: 1. Applies to ML22Q340-NNN / ML22Q341-NNN. |
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