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PIC17CXX Datasheet(PDF) 10 Page - Microchip Technology

Part # PIC17CXX
Description  EPROM Memory Programming Specification
Download  16 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC17CXX Datasheet(HTML) 10 Page - Microchip Technology

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PIC17CXX
DS30139I-page 10
© 1996 Microchip Technology Inc.
5.0
AC/DC CHARACTERISTICS
TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE
Standard Operating Conditions
Operating Temperature:
+10
°C ≤ TA ≤ +70°C, unless otherwise stated, (25°C is recommended)
Operating Voltage:
4.5V
≤ VDD ≤ 5.25V, unless otherwise stated.
Parameter
No.
Sym.
Characteristic
Min.
Typ.
Max.
Units
Conditions/Comments
PD1
VDDP
Supply voltage during pro-
gramming
4.75
5.0
5.25
V
PD2
IDDP
Supply current during pro-
gramming
50
mA
Freq = 10MHz, VDD = 5.5V
Note 3
PD3
VDDV
Supply voltage during verify
VDD
min.
VDD
max.
V
Note 2
PD4
VPP
Voltage on VPP/MCLR pin
during programming
12.75
13.25
V
Note 1
PD6
IPP
Programming current on
VPP/MCLR pin
25
50
mA
Note 3
P1
FOSCP
Osc/clockin frequency dur-
ing programming
4
10
MHz
P2
TCY
Instruction cycle
1
0.4
µsTCY = 4/FOSCP
P3
TirV2tsH
RA0, RA1, RA2, RA3, RA4
setup before TEST
1
µs
P4
TtsH2mcH TEST
↑ to MCLR↑
1
µs
P5
TbcV2irH
RC<7:0>, RB<7:0> valid to
RA1 or RA0
↑ :Address/Data
input setup time
0
µs
P6
TirH2bcl
RA1 or RA0
↑ to RB<7:0>,
RC<7:0> invalid ; Address
data hold time;
10 TCY
µs
P7
T0ckiL2rbc
Z
RT
↓ to RB<7:0>, RC<7:0>
high impedance
8 TCY
P8
T0ckiH2bcV RA1
↑ to data out valid
10 TCY
P9
Tprog
Programming pulse width
10
100
1000
µs
P10
TirH2irL
RA0, RA1 high pulse width
10 TCY
µs
P11
TirL2irH
RA0, RA1 low pulse width
10 TCY
µs
P12
T0ckiV2inL RA1
↑ before INT↓ (to go
from prog cycle to verify w/o
increment)
0
µs
P13
TinL2rtl
RA1 valid after RA0 (to
select increment or no incre-
ment going from program to
verify cycle
10 TCY
µs
P14
Tvpps
VPP setup time before RA0
100
µs Note 1
P15
Tvpph
VPP hold time after INT
0
µs Note 1
P16
TvdV2tsH VDD stable to TEST
10
ms
P17
TrbV2mcH RB input (E1h) valid to VPP/
MCLR
0
µs
P18
TmcH2rbI RB input (E1h) hold after
VPP/MCLR
10 TCY
ns
P19
TvpL2vdL VDD power down after VPP
power down
10
ms
Note 1: VPP/MCLR pin must only be equal to or greater than VDD at times other than programming.
Note 2: Program must be verified at the minimum and maximum VDD limits for the part.
Note 3: These parameters are for design guidance only and are not tested nor characterized.


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