© 1998 Microchip Technology Inc.

Preliminary

DS40197A-page 9

PIC16HV540

TABLE 5-2:

INSTRUCTION SET SUMMARY

Mnemonic,

Operands

Description

Cycles

12-Bit Opcode

Status

Affected Notes

MSb

LSb

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

DECFSZ

INCF

INCFSZ

IORWF

MOVF

MOVWF

NOP

RLF

RRF

SUBWF

SWAPF

XORWF

f,d

f,d

f

–

f, d

f, d

f, d

f, d

f, d

f, d

f, d

f

–

f, d

f, d

f, d

f, d

f, d

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

Move W to f

No Operation

Rotate left f through Carry

Rotate right f through Carry

Subtract W from f

Swap f

Exclusive OR W with f

1

1

1

1

1

1

1(2)

1

1(2)

1

1

1

1

1

1

1

1

1

0001

0001

0000

0000

0010

0000

0010

0010

0011

0001

0010

0000

0000

0011

0011

0000

0011

0001

11df

01df

011f

0100

01df

11df

11df

10df

11df

00df

00df

001f

0000

01df

00df

10df

10df

10df

ffff

ffff

ffff

0000

ffff

ffff

ffff

ffff

ffff

ffff

ffff

ffff

0000

ffff

ffff

ffff

ffff

ffff

C,DC,Z

Z

Z

Z

Z

Z

None

Z

None

Z

Z

None

None

C

C

C,DC,Z

None

Z

1,2,4

2,4

4

2,4

2,4

2,4

2,4

2,4

2,4

1,4

2,4

2,4

1,2,4

2,4

2,4

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

f, b

f, b

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1

1

1 (2)

1 (2)

0100

0101

0110

0111

bbbf

bbbf

bbbf

bbbf

ffff

ffff

ffff

ffff

None

None

None

None

2,4

2,4

LITERAL AND CONTROL OPERATIONS

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

OPTION

RETLW

SLEEP

TRIS

XORLW

k

k

k

k

k

k

k

k

–

f

k

AND literal with W

Call subroutine

Clear Watchdog Timer

Unconditional branch

Inclusive OR Literal with W

Move Literal to W

Load OPTION register

Return, place Literal in W

Go into standby mode

Load TRIS register

Exclusive OR Literal to W

1

2

1

2

1

1

1

2

1

1

1

1110

1001

0000

101k

1101

1100

0000

1000

0000

0000

1111

kkkk

kkkk

0000

kkkk

kkkk

kkkk

0000

kkkk

0000

0000

kkkk

kkkk

kkkk

0100

kkkk

kkkk

kkkk

0010

kkkk

0011

0fff

kkkk

Z

None

None

Z

None

None

None

None

Z

1

3

Note 1: The 9th bit of the program counter will be forced to a '0' by any instruction that writes to the PC except for GOTO.

(See individual device data sheets, Memory Section/Indirect Data Addressing, INDF and FSR Registers)

2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that value

present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven

low by an external device, the data will be written back with a '0'.

3: The instruction TRIS f, where f = 5 or 6 causes the contents of the W register to be written to the tristate

latches of PORTA or B respectively. A '1' forces the pin to a hi-impedance state and disables the output buffers.

4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared

(if assigned to TMR0).