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X28HC256JIZ-12 Datasheet(PDF) 3 Page - Intersil Corporation |
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X28HC256JIZ-12 Datasheet(HTML) 3 Page - Intersil Corporation |
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3 / 19 page  X28HC256 3 FN8108.5 August 27, 2015 Submit Document Feedback Pin Configurations X28HC256 (28 LD FLATPACK, PDIP, SOIC) TOP VIEW X28HC256 (32 LD PLCC, LCC) TOP VIEW A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 A1 NC 4 3 2 1 32 31 30 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 A8 A9 A11 OE A10 OE CE I/O7 I/O6 NC I/O0 A0 A2 A3 A4 A5 A6 Pin Descriptions PIN NAME PIN # PDIP, SOIC PIN # PLCC, LCC DESCRIPTION A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14 10, 9, 8, 7, 6, 5, 4, 3, 25, 24, 21, 23, 2, 26, 1 11, 10, 9, 8, 7, 6, 5, 4, 29, 28, 24, 27, 3, 30, 2 Addresses (A0 to A14) - Address inputs. The address inputs select an 8-bit memory location during a read or write operation. I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7 11, 12, 13, 15 16, 17, 18, 19 13, 14, 15, 18 19, 20, 21, 22 Data In/Data Out (I/O0 to I/O7) - Data input/output- Data is written to or read from the X28HC256 through the I/O pins. WE 27 31 Write Enable (WE) - The Write enable input controls the writing of data to the X28HC256. CE 20 23 Chip Enable (CE) - The Chip enable input must be LOW to enable all read/write operations. When CE is HIGH, power consumption is reduced. OE 22 25 Output Enable (OE) - The output enable input controls the data output buffers, and is used to initiate read operations. VCC 28 32 +5V VSS 14 16 Ground NC - 1, 12, 17, 26 No Connect |
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