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93LC66A Datasheet(PDF) 5 Page - Microchip Technology

Part No. 93LC66A
Description  4K 2.5V Microwire Serial EEPROM
Download  12 Pages
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Maker  MICROCHIP [Microchip Technology]
Homepage  http://www.microchip.com
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93LC66A Datasheet(HTML) 5 Page - Microchip Technology

 
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93LC66A/B
 1998 Microchip Technology Inc.
DS21209C-page 5
3.4
ERASE
The ERASE instruction forces all data bits of the spec-
ified address to the logical “1” state. CS is brought low
following the loading of the last address bit. This falling
edge of the CS pin initiates the self-timed programming
cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical “0” indicates that program-
ming is still in progress. DO at logical “1” indicates that
the register at the specified address has been erased
and the device is ready for another instruction.
3.5
Erase All (ERAL)
The Erase All (ERAL) instruction will erase the entire
memory array to the logical “1” state. The ERAL cycle
is identical to the ERASE cycle except for the different
opcode. The ERAL cycle is completely self-timed and
commences at the falling edge of the CS. Clocking of
the CLK pin is not necessary after the device has
entered the ERAL cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL) and before the entire ERAL cycle is com-
plete.
FIGURE 3-2:
ERASE TIMING
FIGURE 3-3:
ERAL TIMING
CS
CLK
DI
DO
TCSL
CHECK STATUS
1
1
1AN
AN-1
AN-2
•••
A0
TSV
TCZ
BUSY
READY
HIGH-Z
TWC
HIGH-Z
CS
CLK
DI
DO
TCSL
CHECK STATUS
10
0
1
0
X
•••
X
TSV
TCZ
BUSY
READY
HIGH-Z
TEC
HIGH-Z
Guaranteed at Vcc = 4.5V to +6.0V.


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