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93LC66A Datasheet(PDF) 4 Page - Microchip Technology

Part No. 93LC66A
Description  4K 2.5V Microwire Serial EEPROM
Download  12 Pages
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Maker  MICROCHIP [Microchip Technology]
Homepage  http://www.microchip.com
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93LC66A Datasheet(HTML) 4 Page - Microchip Technology

 
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93LC66A/B
DS21209C-page 4
 1998 Microchip Technology Inc.
3.0
FUNCTIONAL DESCRIPTION
Instructions, addresses, and write data are clocked into
the DI pin on the rising edge of the clock (CLK). The DO
pin is normally held in a HIGH-Z state except when
reading data from the device, or when checking the
READY/BUSY status during a programming operation.
The READY/BUSY status can be verified during an
ERASE/WRITE operation by polling the DO pin; DO
low indicates that programming is still in progress, while
DO high indicates the device is ready. The DO will enter
the HIGH-Z state on the falling edge of the CS.
3.1
START Condition
The START bit is detected by the device if CS and DI
are both high with respect to the positive edge of CLK
for the first time.
Before a START condition is detected, CS, CLK, and DI
may change in any combination (except to that of a
START condition), without resulting in any device oper-
ation (ERASE, ERAL, EWDS, EWEN, READ, WRITE,
and WRAL). As soon as CS is high, the device is no
longer in the standby mode.
An instruction following a START condition will only be
executed
if
the
required
amount
of
opcodes,
addresses, and data bits for any particular instruction is
clocked in.
After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become don’t care bits until a new START condition is
detected.
3.2
Data In (DI) Data Out (DO)
It is possible to connect the Data In (DI)and Data Out
(DO)pins together. However, with this configuration, if
A0 is a logic-high level, it is possible for a “bus conflict”
to occur during the “dummy zero” that precedes the
READ operation. Under such a condition the voltage
level seen at Data Out is undefined and will depend
upon the relative impedances of Data Out and the sig-
nal source driving A0. The higher the current sourcing
capability of A0, the higher the voltage at the Data Out
pin.
3.3
Data Protection
During power-up, all programming modes of operation
are inhibited until VCC has reached a level greater than
2.2V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when
Vcc has fallen below 2.2V at nominal conditions.
The ERASE/WRITE Disable (EWDS) and ERASE/
WRITE Enable (EWEN) commands give additional pro-
tection against accidentally programming during nor-
mal operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before any ERASE or WRITE instruction
can be executed.
FIGURE 3-1:
SYNCHRONOUS DATA TIMING
CS
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VOH
VOL
CLK
DI
DO
(READ)
DO
(PROGRAM)
TCSS
TDIS
TCKH
TCKL
TDIH
TPD
TCSH
TPD
TCZ
STATUS VALID
TSV
TCZ
Note:
AC Test Conditions: VIL = 0.4V, VIH = 2.4V.


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