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93C66A Datasheet(PDF) 7 Page - Microchip Technology |
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93C66A Datasheet(HTML) 7 Page - Microchip Technology |
7 / 12 page © 1998 Microchip Technology Inc. Preliminary DS21207B-page 7 93C66A/B 3.8 WRITE The WRITE instruction is followed by 8 bits (93C66A) or 16 bits (93C66B) of data which are written into the specified address. After the last data bit is clocked into the DI pin the self-timed auto-erase and programming cycle begins. The DO pin indicates the READY/BUSY status of the device, if CS is brought high after a minimum of 250 ns low (TCSL) and before the entire write cycle is complete. DO at logical “0” indicates that programming is still in progress. DO at logical “1” indicates that the register at the specified address has been written with the data specified and the device is ready for another instruc- tion. 3.9 Write All (WRAL) The WRAL instruction will write the entire memory array with the data specified in the command. The WRAL cycle is completely self-timed and commences at the rising clock edge of the last data bit. Clocking of the CLK pin is not necessary after the device has entered the WRAL cycle. The WRAL command does include an automatic ERAL cycle for the device. There- fore, the WRAL instruction does not require an ERAL instruction but the chip must be in the EWEN status. The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (TCSL). FIGURE 3-7: WRITE TIMING FIGURE 3-8: WRAL TIMING CS CLK DI DO 1 0 1 An ••• A0 Dx ••• D0 BUSY READY HIGH-Z HIGH-Z Twc TCSL TCZ TSV CS CLK DI DO HIGH-Z 1 0 0 01 X ••• X Dx ••• D0 HIGH-Z BUSY READY TWL TCSL TSV TCZ |
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