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24LC21A-SN Datasheet(PDF) 9 Page - Microchip Technology |
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24LC21A-SN Datasheet(HTML) 9 Page - Microchip Technology |
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9 / 16 page  2003 Microchip Technology Inc. DS21160F-page 9 24LC21A 4.0 WRITE OPERATION 4.1 Byte Write Following the start signal from the master, the slave address (four bits), three zero bits (000) and the R/W bit which is a logic low are placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an Acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the word address and will be written into the address pointer of the 24LC21A. After receiving another acknowledge signal from the 24LC21A the master device will transmit the data word to be written into the addressed memory location. The 24LC21A acknowledges again and the master generates a Stop condition. This initiates the internal write cycle, and during this time the 24LC21A will not generate acknowledge signals (Figure 4-1). It is required that VCLK be held at a logic high level during command and data transfer in order to program the device. This applies to both byte write and page write operation. Note, however, that the VCLK is ignored during the self-timed program operation. Changing VCLK from high-to-low during the self-timed program operation will not halt programming of the device. 4.2 Page Write The write control byte, word address and the first data byte are transmitted to the 24LC21A in the same way as in a byte write. But instead of generating a Stop condition the master transmits up to eight data bytes to the 24LC21A which are temporarily stored in the on- chip page buffer and will be written into the memory after the master has transmitted a Stop condition. After the receipt of each word, the three lower order address pointer bits are internally incremented by one. The higher order five bits of the word address remains constant. If the master should transmit more than eight words prior to generating the Stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the Stop condition is received an internal write cycle will begin (Figure 4-3). It is required that VCLK be held at a logic high level during command and data transfer in order to program the device. This applies to both byte write and page write operation. Note, however, that the VCLK is ignored during the self-timed program operation. Changing VCLK from high-to-low during the self-timed program operation will not halt programming of the device. Note: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multi- ples of the page buffer size (or ‘page size’) and end at addresses that are integer multiples of [page size - 1]. If a Page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. |
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