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SY88943V Datasheet(PDF) 1 Page - Micrel Semiconductor

Part No. SY88943V
Description  5V/3.3V 2.5Gbps LIMITING POST AMPLIFIER WITH SIGNAL DETECT
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Maker  MICREL [Micrel Semiconductor]
Homepage  http://www.micrel.com
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SY88943V Datasheet(HTML) 1 Page - Micrel Semiconductor

   
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DESCRIPTION
s 3.3V and 5V power supply options
s Up to 2.5Gbps operation
s Low noise
s Chatter-fee signal detect (SD) generation
s Open collector TTL signal detect (SD) output
s TTL EN input
s Differential PECL inputs for data
s Single power supply
s Designed for use with Micrel-Synergy laser diode
driver and controller
s Available in a tiny (3mm) 10-pin MSOP
The SY88943V limiting post amplifier with its high gain
and wide bandwidth is ideal for use as a post amplifier in
fiber-optic receivers with data rates up to 2.5Gbps.
Signals as small as 5mVp-p can be amplified to drive
devices with PECL inputs. The SY88943V generates a
chatter-free Signal Detect (SD) open collector TTL output.
The SY88943V incorporates a programmable level detect
function to identify when the input signal has been lost.
The SD output will change from logic “HIGH” to logic “LOW”
when input signal is smaller than the swing set by SD
LVL.
This information can be fed back to the EN input of the
device to maintain stability under loss of signal condition.
Using SD
LVL pin, the sensitivity of the level detection can
be adjusted. The SD
LVL voltage can be set by connecting
a resistor divider between V
CC and VREF as shown in Figure
3. Figure 4, 5, 6, and 7 show the relationship between
input level sensitivity and the voltage set on SD
LVL.
The SD output is a TTL open collector output that
requires a pull-up resistor for proper operation, Figure 1.
SY88943V
SD
4.7k
Ω to 10kΩ
VCC
Figure 1. SD Output with Desired Rise Time
FEATURES
5V/3.3V 2.5Gbps
LIMITING POST AMPLIFIER
WITH SIGNAL DETECT
SY88943V
APPLICATIONS
s 1.25Gbps and 2.5Gbps ethernet
s 531Mbps, 1062Mbps and 2.12Gbps Fibre Channel
s 622Mbps SONET
s Gigabit interface converter
s 2.5Gbps SDH/SONET
s 2.5Gbps proprietary links
PIN CONFIGURATION
BLOCK DIAGRAM
1
EN
DIN
/DIN
VREF
SDLVL
10 VCC
DOUT
/DOUT
SD
GND
9
8
7
6
2
3
4
5
MSOP
K10-1
Limiting
Amplifer
ECL
Buffer
GND
Enable
Level
Detect
EN
SD
DOUT
/DOUT
DIN
/DIN
VREF
VCC
SDLVL
1
Rev.: B
Amendment: /0
Issue Date:
August 2000


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