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ISL78206AVEZ Datasheet(PDF) 2 Page - Intersil Corporation
INTERSIL [Intersil Corporation]
ISL78206AVEZ Datasheet(HTML) 2 Page - Intersil Corporation
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March 25, 2015
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(20 LD HTSSOP)
Functional Pin Description
This pin is used as the ground connection of the power flow, including the driver.
This pin provides bias voltage to the high-side MOSFET driver. A bootstrap circuit is used to create a voltage suitable to drive
the internal N-channel MOSFET. The boot charge circuitries are integrated inside of the IC. No external boot diode is needed.
A 1µF ceramic capacitor is recommended to be used between the BOOT and PHASE pin.
Connect the input rail to these pins that are connected to the drain of the integrated high-side MOSFET, as well as the source
for the internal linear regulator that provides the bias of the IC.
With the part switching, the operating input voltage applied to the VIN pins must be under 40V. This recommendation allows
for short voltage ringing spikes (within a couple of ns time range) due to switching while not exceeding Absolute Maximum
This pin provides the return path for the control and monitor portions of the IC.
This pin is the output of the internal linear regulator that supplies the bias for the IC, including the driver. A minimum 4.7µF
decoupling ceramic capacitor is recommended between VCC to ground.
The controller is enabled when this pin is pulled HIGH or left floating. The IC is disabled when this pin is pulled LOW. Range:
0V to 5.5V.
Tying this pin to VCC, or GND, or leaving it open will force the IC to have 500kHz switching frequency. The oscillator switching
frequency can also be programmed by adjusting the resistor from this pin to GND.
Connect a capacitor from this pin to ground. This capacitor, along with an internal 5µA current source, sets the soft-start
interval of the converter. Also, this pin can be used to track a ramp on this pin.
This pin is the inverting input of the voltage feedback error amplifier. With a properly selected resistor divider connected from
to FB, the output voltage can be set to any voltage between the input rail (reduced by maximum duty cycle and voltage
drop) and the 0.8V reference. Loop compensation is achieved by connecting an RC network across COMP and FB. The FB pin
is also monitored for overvoltage events.
Output of the voltage feedback error amplifier.
Programmable current limit pin. With this pin connected to VCC pin, or to GND, or left open, the current limit threshold is set
to a default of 3.6A; the current limit threshold can be programmed with a resistor from this pin to GND.
Digital ground pin. Connect to SGND at quiet ground copper plane.
PGOOD is an open drain output and pull up this pin with a resistor to VCC for proper function. PGOOD will be pulled low
under the events when the output is out of regulation (OV or UV) or EN pin is pulled low. PGOOD rising has a fixed 128
These pins are the PHASE nodes that should be connected to the output inductor. These pins are connected to the source of
the high side N-channel MOSFET.
This pin can be used to synchronize two or more ISL78206 controllers. Multiple ISL78206s can be synchronized with their
SYNC pins connected together. 180 degree phase shift is automatically generated between the master and slave ICs.
The internal oscillator can also lock to an external frequency source applied to this pin with square pulse waveform (with
frequency 10% higher than the IC’s local frequency, and pulse width higher than 150ns).
This pin should be left floating if not used.
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