Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

ISL78206AVEZ Datasheet(PDF) 17 Page - Intersil Corporation

Part No. ISL78206AVEZ
Description  40V 2.5A Buck Controller with Integrated High-side 40V 2.5A Buck Controller with Integrated High-side
Download  19 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
Logo 

ISL78206AVEZ Datasheet(HTML) 17 Page - Intersil Corporation

 
Zoom Inzoom in Zoom Outzoom out
 17 / 19 page
background image
ISL78206
17
FN8618.2
March 25, 2015
Submit Document Feedback
Select the crossover frequency to be 35kHz. Since the output
capacitors are all ceramics, use Equations 22 and 23 on page 16
to derive R3 to be 20k and C3 to be 470pF.
Then use Equations 24 and 25 on page 16 to calculate C1 to be
180pF and R2 to be 12.7k. Select 150pF for C1 and 15k for R2.
There is approximately 30pF parasitic capacitance between the
COMP to FB pins that contributes to a high frequency pole. Any
extra external capacitor is not recommended between COMP
and FB.
Figure 24 shows the simulated bode plot of the loop. It is shown
that it has 26kHz loop bandwidth with 70° phase margin and
H28dB gain margin.
Layout Suggestions
1. Place the input ceramic capacitors as close as possible to the
IC VIN pin and power ground connecting to the power MOSFET
or diode. Keep this loop (input ceramic capacitor, IC VIN pin
and MOSFET/Diode) as tiny as possible to achieve the least
voltage spikes induced by the trace parasitic inductance.
2. Place the input aluminum capacitors close to the IC VIN pin.
3. Keep the phase node copper area small, but large enough to
handle the load current.
4. Place the output ceramic and aluminum capacitors also close
to the power stage components.
5. Put vias (20 recommended) in the bottom pad of the IC. The
bottom pad should be placed in the ground copper plane with
area as large as possible in multiple layers to effectively
reduce the thermal impedance.
6. Place the 4.7µF ceramic decoupling capacitor at the VCC pin
and as close as possible to the IC. Put multiple vias (≥3) close
to the ground pad of this capacitor.
7. Keep the bootstrap capacitor close to the IC.
8. Keep the LGATE drive trace as short as possible and try to
avoid using via in LGATE drive path to achieve the lowest
impedance.
9. Place the positive voltage sense trace close to the load for
tighter regulation.
10. Put all the peripheral control components close to the IC.
FIGURE 24. SIMULATED LOOP GAIN
0
20
40
60
80
LOOP GAIN
-60
-40
-20
100
1k
10k
100k
1M
FREQUENCY (Hz)
80
100
120
140
160
180
0
20
40
60
100
1k
10k
100k
1M
FREQUENCY (Hz)
PHASE MARGIN
FIGURE 25. PCB VIA PATTERN


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn