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ISL78206AVEZ Datasheet(PDF) 15 Page  Intersil Corporation 

ISL78206AVEZ Datasheet(HTML) 15 Page  Intersil Corporation 
15 / 19 page ISL78206 15 FN8618.2 March 25, 2015 Submit Document Feedback Regarding transient response needs, a good starting point is to determine the allowable overshoot in VOUT if the load is suddenly removed. In this case, energy stored in the inductor will be transferred to COUT causing its voltage to rise. After calculating capacitance required for both ripple and transient needs, choose the larger of the calculated values. The following equation determines the required output capacitor value in order to achieve a desired overshoot relative to the regulated voltage. Where VOUTMAX/VOUT is the relative maximum overshoot allowed during the removal of the load. Input Capacitors Depending upon the system input power rail conditions, the aluminum electrolytic type capacitor is normally needed to provide the stable input voltage and restrict the switching frequency pulse current in small areas over the input traces for better EMC performance. The input capacitor should be able to handle the RMS current from the switching power devices. Ceramic capacitors must be used at the VIN pin of the IC and multiple capacitors, including 1µF and 0.1µF, are recommended. Place these capacitors as closely as possible to the IC. Output Inductor The inductor value determines the converter’s ripple current. Choosing an inductor current requires a somewhat arbitrary choice of ripple current, I. A reasonable starting point is 30% to 40% of total load current. The inductor value can then be calculated using Equation 7: Increasing the value of inductance reduces the ripple current and thus ripple voltage. However, the larger inductance value may reduce the converter’s response time to a load transient. The inductor current rating should be such that it will not saturate in overcurrent conditions. Low Side Power MOSFET In synchronous buck application, a power N MOSFET is needed as the synchronous low side MOSFET and a good one should have low Qgd, low rDS(ON) and small Rg (Rg_typ <1.5Ω recommended). Vgth_min is recommended to be or higher than 1.2V. A good example is SQS462EN. In synchronous buck configuration, a 5.1k or smaller value resistor has to be added to connect LGATE to ground to avoid falsely turnon of LGATE caused by coupling noise. Output Voltage Feedback Resistor Divider The output voltage can be programmed down to 0.8V by a resistor divider from VOUT to FB, according to Equation 8. In applications requiring the least input quiescent current, large resistors should be used for the divider to keep its leakage current low. Generally, a resistor value of 10k to 300k can be used for the upper resistor. Loop Compensation Design The ISL78206 uses constant frequency peak current mode control architecture to achieve fast loop transient response. An accurate current sensing pilot device in parallel with the upper MOSFET is used for peak current control signal and overcurrent protection. The inductor is not considered as a state variable since its peak current is constant, and the system becomes single order system. It is much easier to design the compensator to stabilize the loop compared with voltage mode control. Peak current mode control has inherent input voltage feedforward function to achieve good line regulation. Figure 22 shows the small signal model of a buck regulator. PWM Comparator Gain Fm The PWM comparator gain Fm for peak current mode control is given by Equation 9: Where Se is the slew rate of the slope compensation and Sn is given by Equation 10. Where Rt is the gain of the current amplifier. Current Sampling Transfer Function He(S) In current loop, the current signal is sampled every switching cycle. It has the following transfer function in Equation 11: Where Qn and n are given by (EQ. 6) COUT IOUT2*L VOUT2* VOUTMAX VOUT 2 1 –  = (EQ. 7) L VIN VOUT – Fs I  VOUT VIN  = VOUT 0.8 1 RUP RLOW  + = (EQ. 8) d Vin d IL in in i L + 1:D L i Co Rc Av(S) d comp v R T Fm He(S) + T i(S) o v Tv(S) I LP + 1:D Rc Ro Av(S) R T Fm He(S) T i(S) o T(S) ^ ^ V ^ ^ ^ ^ ^ ^ FIGURE 22. SMALL SIGNAL MODEL OF BUCK REGULATOR RLP Fm dˆ vˆcomp  1 Se Sn + T s  == (EQ. 9) Sn Rt Vin Vo – LP  = (EQ. 10) He S S 2 n 2  = S nQn  1 ++ (EQ. 11) Qn 2  – = n f s = 
