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ISL78206AVEZ Datasheet(PDF) 13 Page - Intersil Corporation
INTERSIL [Intersil Corporation]
ISL78206AVEZ Datasheet(HTML) 13 Page - Intersil Corporation
/ 19 page
March 25, 2015
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With the high side MOSFET integrated, the maximum current
that the ISL78206 can support is decided by the package and
many operating conditions, including input voltage, output
voltage, duty cycle, switching frequency and temperature, etc.
From the thermal perspective, the die temperature shouldn’t be
above +125°C with the power loss dissipated inside of the IC.
Figures 10 and 11 on page 9 show the thermal performance of
this part operating in buck at different conditions. Figure 10
shows 2A buck applications under +25°C still air conditions.
(5V, 12V, 20V) applications thermal data are
shown over V
range at +25°C and still air. The temperature rise
data in Figure 10 can be used to estimate the die temperature at
different ambient temperatures under various operating
conditions. Note that more temperature rise is expected at higher
ambient temperature due to more conduction loss caused by
increase. Figure 11 shows 5V output applications'
thermal performance under various output current and input
voltage. It shows the temperature rise trend with load and V
changes. The part can output 2.5A under typical application
5V, 500kHz, still air and +85°C
ambient conditions). The output current should be derated under
any conditions, causing the die temperature to exceed +125°C.
Basically, the die temperature is equal to the sum of the ambient
temperature and the temperature rise resulting from the power
dissipated from the IC package with a certain junction to
ambient thermal impedance
. The power dissipated in the IC
is related to the MOSFET switching loss, conduction loss and the
internal LDO loss. Besides the load, these losses are also related
to input voltage, output voltage, duty cycle, switching frequency
and temperature. With the exposed pad at the bottom, the heat
of the IC mainly goes through the bottom pad and
is highly related to layout and air flow
conditions. In layout, multiple vias (20 recommended) are
strongly recommended in the IC bottom pad. In addition, the
bottom pad with its vias should be placed in the ground copper
plane with an area as large as possible connected through
multiple layers. The
can be reduced further with air flow.
For applications with high output current and bad operating
conditions (compact board size, high ambient temperature, etc.),
synchronous buck is highly recommended since the external
low-side MOSFET generates smaller heat than external low-side
power diode. This helps to reduce PCB temperature rise around
the ISL78206 and less junction temperature rise.
Oscillator and Synchronization
The oscillator has a default frequency of 500kHz with the FS pin
connected to VCC, or ground, or floating. The frequency can be
programmed to any frequency between 200kHz and 2.2MHz with
a resistor from the FS pin to GND.
The SYNC pin is bidirectional and it outputs the IC’s default or
programmed local clock signal when it’s free running. The IC
locks to an external clock injected to SYNC pin (external clock
frequency recommended to be 10% higher than the free running
frequency). The delay from the rising edge of the external clock
signal to the PHASE rising edge is half of the free running switching
period pulse 220ns, (0.5Tsw +220ns). The maximum external clock
frequency is recommended to be 1.6 of the free running frequency.
With the SYNC pins simply connected together, multiple
ISL78206s can be synchronized. The slave ICs automatically
have a 180 degree phase shift with respect to the master IC.
The PGOOD pin is output of an open drain transistor (refer to
“Block Diagram” on page 4). An external resistor is required to be
pulled up to VCC for proper PGOOD function. At startup, PGOOD
will be turned HIGH (internal PGOOD open drain transistor is
turned off) with 128 cycles delay after soft-start is finished
(soft-start ramp reaches 1.02V) and FB voltage is within OV/UV
window (90%REF < FB < 110%REF).
At normal operation, PGOOD will be pulled low with 1 cycle
(minimum) and 6 cycles (maximum) delay if any of the OV
(110%) or UV (90%) comparator is tripped. The PGOOD will be
released HIGH with 128 cycles delay after FB recovers to be
within OV/UV window (90%REF < FB < 110%REF). When EN is
pulled low or VCC is below POR, PGOOD is pulled low with no
In the case when the PGOOD pin is pulled up by external bias
supply instead of VCC of itself, when the part is disabled, the
internal PGOOD open drain transistor is off, the external bias
supply can charge PGOOD pin HIGH. This should be known as false
PGOOD reporting. At start-up when VCC rise from 0, PGOOD will be
pulled low when VCC reaches 1V. After EN pulled low and VCC
falling, PGOOD internal open drain transistor will open with high
impedance when VCC falls below 1V. The time between EN pulled
low and PGOOD OPEN depends on the VCC falling time to 1V.
145000 16 FS
FIGURE 20. R
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