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ISL78206AVEZ Datasheet(PDF) 12 Page - Intersil Corporation

Part No. ISL78206AVEZ
Description  40V 2.5A Buck Controller with Integrated High-side 40V 2.5A Buck Controller with Integrated High-side
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home

ISL78206AVEZ Datasheet(HTML) 12 Page - Intersil Corporation

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March 25, 2015
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Functional Description
Initially, the ISL78206 continually monitors the voltage at the EN
pin. When the voltage on the EN pin exceeds its rising threshold,
the internal LDO will start-up to build up VCC. After Power-On
Reset (POR) circuits detect that the VCC voltage has exceeded
the POR threshold, the soft-start will be initiated.
The soft-start (SS) ramp is built up in the external capacitor on
the SS pin that is charged by an internal 5µA current source.
The SS ramp starts from 0 to voltage above 0.8V. Once SS
reaches 0.8V, the bandgap reference takes over and the IC gets
into steady state operation. The soft-start time is referring to the
duration for SS pin ramps from 0 to 0.8V while output voltage
ramps up with the same rate from 0 to target regulated voltage.
The required capacitance at SS pin can be calculated from
Equation 1.
The SS plays a vital role in the hiccup mode of operation. The IC
works as cycle-by-cycle peak current limiting at over load
condition. When a harsh condition occurs and the current in the
upper side MOSFET reaches the second overcurrent threshold,
the SS pin is pulled to ground and a dummy soft-start cycle is
initiated. At dummy SS cycle, the current to charge the soft-start
cap is cut down to 1/5 of its normal value. Therefore, a dummy
SS cycle takes 5 times that of the regular SS cycle. During the
dummy SS period, the control loop is disabled and there is no
PWM output. At the end of this cycle, it will start the normal SS.
The hiccup mode persists until the second overcurrent threshold
is no longer reached.
The ISL78206 is capable of starting up with pre-biased output.
PWM Control
The ISL78206 employs the peak current mode PWM control for
fast transient response and cycle-by-cycle current limiting. See
the “Block Diagram” on page 4.
The PWM operation is initialized by the clock from the oscillator.
The upper MOSFET is turned on by the clock at the beginning of a
PWM cycle and the current in the MOSFET starts to ramp up.
When the sum of the current sense signal and the slope
compensation signal reaches the error amplifier output voltage
level, the PWM comparator is triggered to shut down the PWM
logic to turn off the high side MOSFET. The high side MOSFET
stays off until the next clock signal starts.
The output voltage is sensed by a resistor divider from VOUT to FB
pin. The difference between the FB voltage and 0.8V reference is
amplified and compensated to generate the error voltage signal
at the COMP pin. Then the COMP pin signal is compared with the
current ramp signal to shut down the PWM.
Synchronous and Non-synchronous Buck
The ISL78206 supports both synchronous and non-synchronous
buck operations.
In synchronous buck configuration, a 5.1k or smaller value
resistor has to be added to connect LGATE to ground to avoid
falsely turn-on of LGATE caused by coupling noise.
For a non-synchronous buck operation when a power diode is
used as the low-side power device, the LGATE driver can be
disabled with LGATE connected to VCC (before IC start-up). For
non-synchronous buck, the phase node will show oscillations
after high-side turns off (as shown in Figure 18 - blue trace). This
is normal due to the oscillations among the parasitic capacitors
at phase node and output inductor. An RC snubber (suggesting
200Ω and 2.2nF as typical) at phase node can reduce this
Input Voltage
With the part switching, the operating input voltage applied to
the VIN pins must be under 40V. This recommendation allows for
short voltage ringing spikes (within a couple of ns time range)
due to switching while not exceeding Absolute Maximum
The lowest IC operating input voltage (VIN pin) depends on VCC
voltage and the Rising and Falling VCC POR Threshold in the
Electrical Specifications table on page 6. At IC startup, when VCC
is just over the rising POR threshold, there is no switching yet
before the soft-start starts. Therefore, the IC minimum start-up
voltage on VIN pin is 3.05V (MAX of Rising VCC POR). When the
soft-start is initiated, the regulator is switching and the dropout
voltage across the internal LDO increases due to driving current.
Thus the IC VIN pin shutdown voltage is related to driving current
and VCC POR falling threshold. The internal upper side MOSFET
has typical 10nC gate drive. For a typical example of synchronous
buck with 4nC lower MOSFET gate drive and 500kHz switching
frequency, the driving current is 7mA total causing 70mV drop
across internal LDO under 3V VIN. Then the IC shutdown voltage
on the VIN pin is 2.87V (2.8V + 0.07V). In practical design, extra
room should be taken into account with concerns of voltage
spikes at VIN.
Output Voltage
The output voltage can be programmed down to 0.8V by a
resistor divider from VOUT to FB. For buck, the maximum
achievable voltage is (VIN*DMAX -VDROP), where VDROP is the
voltage drop in the power path, including mainly the MOSFET
rDS(ON) and inductor DCR. The maximum duty cycle DMAX is
decided by (1 - Fs * tMIN(OFF)).
6.5 tSS S
(EQ. 1)

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