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ISL78201AVEZ Datasheet(PDF) 3 Page - Intersil Corporation |
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ISL78201AVEZ Datasheet(HTML) 3 Page - Intersil Corporation |
3 / 23 page ISL78201 3 FN8615.1 March 31, 2015 Submit Document Feedback PGOOD 15 PGOOD is an open drain output and pull-up this pin with a resistor to VCC for proper function. PGOOD will be pulled low under the events when the output is out of regulation (OV or UV) or EN pin is pulled low. PGOOD rising has a fixed 128 cycles delay. PHASE 16, 17 These pins are the PHASE nodes that should be connected to the output inductor. These pins are connected to the source of the high-side N channel MOSFET. EXT_BOOST 18 This pin is used to set boost mode and monitor the battery voltage that is the input of the boost converter. After VCC POR, the controller will detect the voltage on this pin, if voltage on this pin is below 200mV, the controller is set in synchronous/non-synchronous buck mode and latch in this state unless VCC is below the POR falling threshold; if the voltage on this pin after VCC POR is above 200mV, the controller is set in boost mode and latch in this state. In boost mode, this pin is used to monitor input voltage through a resistor divider. By setting the resistor divider, the high threshold and hysteresis can be programmed. When voltage on this pin is above 0.8V, the PWM output (LGATE) for the boost converter is disabled, and when voltage on this pin is below 0.8V minus the hysteresis, the boost PWM is enabled. In boost mode operation, PFM is disabled when boost PWM is enabled. Check Boost Mode Operation in the “Functional Description” on page 14 for more details. SYNC 19 This pin can be used to synchronize two or more ISL78201 controllers. Multiple ISL78201s can be synchronized with their SYNC pins connected together. 180 degree phase shift is automatically generated between the master and slave ICs. The internal oscillator can also lock to an external frequency source applied on this pin with square pulse waveform (with frequency 10% higher than the IC’s local frequency, and pulse width higher than 150ns). This pin should be left floating if not used. Range: 0V to 5.5V. LGATE 20 In synchronous buck mode, this pin is used to drive the lower side MOSFET to improve efficiency. A 5.1k or smaller value resistor has to be added to connect LGATE to ground to avoid falsely turn-on of LGATE caused by coupling noise. In non-synchronous buck when a diode is used as the bottom side power device, this pin should be connected to VCC through a resistor (less than 5k) before VCC start-up to have low-side driver (LGATE) disabled. In boost mode, it can be used to drive the boost power MOSFET. The boost control PWM is the same with the buck control PWM. PAD 21 Bottom thermal pad. It is not connected to any electrical potential of the IC. In layout it must be connected to PCB ground copper plane with an area as large as possible to effectively reduce the thermal impedance. Functional Pin Description (Continued) PIN NAME PIN # DESCRIPTION Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING TEMP. RANGE (°C) PACKAGE (RoHS Compliant) PKG. DWG. # ISL78201AVEZ 78201 AVEZ -40 to +105 20 Ld HTSSOP M20.173A ISL78201EVAL1Z Evaluation Board NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL78201. For more information on MSL please see techbrief TB363. |
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