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SY10H842 Datasheet(PDF) 1 Page - Micrel Semiconductor |
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SY10H842 Datasheet(HTML) 1 Page - Micrel Semiconductor |
1 / 6 page Pin Function GT TTL Ground (0V) VT TTL VCC (+5.0V) VE ECL VCC (+5.0V) GE ECL Ground (0V) D, D Signal Input (PECL) VBB VBB Reference Output (PECL) Q0 - Q3 Signal Outputs (TTL) EN Enable Input (PECL) DESCRIPTION FEATURES ClockWorks™ SY10H842 SY100H842 s Translates positive ECL-to-TTL (PECL-to-TTL) s 300ps pin-to-pin skew s 500ps part-to-part skew s Differential internal design for increased noise immunity and stable threshold inputs s VBB reference output s Single supply s Enable input s Extra TTL and ECL power/ground pins to reduce cross-talk/noise s High drive capability: 24mA each output s Fully compatible with industry standard 10K, 100K I/O levels s Available in 16-pin SOIC package The SY10/100H842 are single supply, low skew translating 1:4 clock drivers. The devices feature a 24mA TTL output stage, with AC performance specified into a 50pF load capacitance. A HIGH on the enable pin (EN) forces all outputs LOW. As frequencies increase to 40MHz and above, precise timing and shaping of clock signals becomes extremely important. The H842 solves several clock distribution problems such as minimizing skew 300ps), maximizing clock fanout (24mA drive), and precise duty cycle control through a proprietary differential internal design. The 10K version is compatible with 10KH ECL logic levels. The 100K version is compatible with 100K levels. PIN CONFIGURATION SINGLE SUPPLY QUAD PECL-TO-TTL OUTPUT ENABLE PIN NAMES BLOCK DIAGRAM D D Q0 Q1 Q2 Q3 VBB EN ECL Input TTL Outputs Rev.: E Amendment: /1 Issue Date: August, 1999 GT Q3 SOIC Z16-1 116 GT 2 15 GE Q2 314 VE VT 4 13 VT 512 Q1 6 11 VBB GT 710 GT Q0 8 9 EN D D 1 |
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