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SY100H641LJC Datasheet(PDF) 1 Page - Micrel Semiconductor |
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SY100H641LJC Datasheet(HTML) 1 Page - Micrel Semiconductor |
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1 / 5 page  DESCRIPTION FEATURES ClockWorks™ PRELIMINARY SY10H641L SY100H641L s 3.3V power supply s PECL-to-TTL version of popular ECLinPS E111 s Guaranteed low skew specification s Latched input s Differential ECL internal design s VBB output for single-ended operation s Reset/enable s Extra TTL and ECL power/ground pins s Choice of ECL compatibility: MECL 10KH (10Hxxx) or 100K (100Hxxx) s Available in 28-pin PLCC package The SY10/100H641L are single supply, low skew translating 1:9 clock drivers. Devices in the Micrel- Synergy H600 translator series utilize the 28-lead PLCC for optimal power pinning, signal flow-through and electrical performance. The devices feature a 24mA TTL output stage with AC performance specified into a 20pF load capacitance. A latch is provided on-chip. When LEN is LOW (or left open, in which case it is pulled LOW by the internal pull- downs), the latch is transparent. A HIGH on the enable pin (/EN) forces all outputs LOW. The 10H version is compatible with MECL 10KH ECL logic levels. The 100H version is compatible with 100K levels. 3.3V SINGLE SUPPLY 1:9 PECL-TO-TTL 18 17 16 15 14 13 12 56789 10 11 26 27 28 1 2 3 4 TOP VIEW PLCC 25 24 23 22 21 20 19 GT Q5 VT Q4 VT Q3 GT VBB D VE LEN GE D EN PIN CONFIGURATION BLOCK DIAGRAM D Q0 Q1 Q2 Q3 VBB EN D Q4 Q5 Q6 Q7 Q8 LEN DQ PECL Input TTL Outputs Pin Function GT TTL Ground (0V) VT TTL VCC (+3.0V) VE ECL VCC (+3.0V) GE ECL Ground (0V) D, /D Signal Input (PECL) VBB VBB Reference Output (PECL) Q0 – Q8 Signal Outputs (TTL) /EN Enable Input (PECL) LEN Latch Enable Input (PECL) PIN NAMES 1 Rev.: D Amendment: /0 Issue Date: May 2000 |
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